CD40174BCM ,Hex D-Type Flip-FlopCD40174BC Hex D-Type Flip-FlopOctober 1987Revised January 2004CD40174BCHex D-Type Flip-Flop
CD40174BCMX , Hex D-Type Flip-FlopFeaturesThe CD40174BC consists of six positive-edge triggered D- Wide supply voltage range: 3V to ..
CD40174BCN ,Hex D-Type Flip-FlopFeaturesThe CD40174BC consists of six positive-edge triggered D-
CD40174BCM-CD40174BCN
Hex D-Type Flip-Flop
CD40174BC Hex D-Type Flip-Flop October 1987 Revised January 2004 CD40174BC Hex D-Type Flip-Flop General Description Features The CD40174BC consists of six positive-edge triggered D-Wide supply voltage range: 3V to 15V type flip-flops; the true outputs from each flip-flop are exter-High noise immunity: 0.45 V (typ.) DD nally available. Low power TTL compatibility: All flip-flops are controlled by a common clock and a com- fan out of 2 driving 74L or 1 driving 74 LS mon clear. Information at the D inputs meeting the set-up Equivalent to MC14174B time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing opera-Equivalent to MM74C174 tion, enabled by a negative pulse at Clear input, clears all Q outputs to logical “0”. All inputs are protected from static discharge by diode clamps to V and V . DD SS Ordering Code: Order Number Package Number Package Description CD40174BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD40174BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table CD40174B Inputs Outputs Clear Clock D Q Q LX X L H H ↑ HH L H ↑ LL H HH X NC NC HL X NC NC H = HIGH Level L = LOW Level X = Irrelevant ↑ = Transition from LOW-to-HIGH level NC = No change Top View © 2004 DS005987
