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CD4014-CD4014BCN
8-Stage Static Shift Register
CD4014BC 8-Stage Static Shift Register October 1987 Revised January 1999 CD4014BC 8-Stage Static Shift Register All inputs are protected against static discharge with diodes General Description to V and V . DD SS The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individ- Features ual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have � Wide supply voltage range: 3.0V to 15V equal source and sink current capabilities and conform to � High noise immunity: 0.45 V (typ.) DD standard “B” series output drive. � Low power TTL compatibility: Fan out of 2 driving 74L When the parallel/serial control input is in the logical “0” or 1 driving 74LS state, data is serially shifted into the register synchronously � 5V–10V–15V parametric ratings with the positive transition of the clock. When the parallel/ serial control input is in the logical “1” state, data is jammed � Symmetrical output characteristics into each stage of the register synchronously with the posi- � Maximum input leakage: tive transition of the clock. 1 μA at 15V over full temperature range Ordering Code: Order Number Package Number Package Description CD4014BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4014BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “x” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP Parallel/ CL Serial Q1 Serial PI 1 PI n Q n (Note 1) Input (Internal) Control X 1 0 000 X 1 1 010 X 1 0 101 X 1 1 111 00 X X 0 Q n−1 10 X X 1 Q n−1 XX X X Q1 Q n X = Don't care case No Change Note 1: Level change Top View © 1999 DS005947.prf
