CD4013BM96 ,CMOS Dual D-Type Flip FlopMaximum Ratings(1)over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT(2) ..
CD4013BM96G4 ,CMOS Dual D-Type Flip Flop 14-SOIC -55 to 125Features... 18 Application and Implementation...... 112 Applications..... 18.1 Application Informat ..
CD4013BMG4 ,CMOS Dual D-Type Flip Flop 14-SOIC -55 to 125Features 3 DescriptionThe CD4013B device consists of two identical,1• Asynchronous Set-Reset Capabi ..
CD4013BNSR ,CMOS Dual D-Type Flip Flop SCHS023E–NOVEMBER 1998–REVISED SEPTEMBER 20165 Pin Configuration and FunctionsD, J, N, NS, PW Pack ..
CD4013BPW ,CMOS Dual D-Type Flip FlopFeatures... 18 Application and Implementation...... 112 Applications..... 18.1 Application Informat ..
CD4013BPWR ,CMOS Dual D-Type Flip FlopBlock Diagram... 10Information..... 147.3 Feature Description ... 104 Revision HistoryChanges from ..
CDSOT23-SM712 , Bus-Polarity Correcting RS-485 Transceiver With IEC-ESD Protection
CDSOT23-SM712 , Bus-Polarity Correcting RS-485 Transceiver With IEC-ESD Protection
CDSOT23-SR724 , CDSOT23-SR724 - Steering Diode Array
CDSOT23-SRV05-4 , CDSOT23-SRV05-4 - Steering Diode TVS Array Combo
CDSS4148 , SMD Switching Diode
CDSU4148 , SMD Switching Diode
CD4013B-CD4013BE-CD4013BEE4-CD4013BM-CD4013BM96-CD4013BM96G4-CD4013BMG4-CD4013BNSR-CD4013BPW-CD4013BPWR
CMOS Dual D-Type Flip Flop
VDD
VSS
4 (10)
RESET
5 (9)
DATA
MASTER SECTION
SLAVE SECTION
All inputs are protected by
CMOS protection network 100 nAat18V and 25°C Noise Margin (Over Full Package Temperature
Range): 1Vat VDD=5V 2Vat VDD=10V 2.5Vat VDD=15V
Applications Power Delivery Grid Infrastructure Medical, Healthcare, and Fitness Body Electronics and Lighting Building Automation Telecom Infrastructure Test and Measurement
clock pulse. Settingor resettingis independentof the
clock andis accomplishedbya high level on the set reset line, respectively.
The CD4013B types are suppliedin 14-pin dual-in-
line plastic packages (E suffix), 14-pin small-outline
packages (M, MT, M96, and NSR suffixes), and
14-pin thin shrink small-outline packages (PW and
PWR suffixes).
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram
