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CBT3253ADPHILIPSN/a601avaiDual 1-of-4 FET multiplexer/demultiplexer
CBT3253APWPHILIPSN/a267avaiDual 1-of-4 FET multiplexer/demultiplexer


CBT3253AD ,Dual 1-of-4 FET multiplexer/demultiplexerLogic diagramCBT3253A All information provided in this document is subject to legal disclaimers. N ..
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CBT3253AD-CBT3253APW
Dual 1-of-4 FET multiplexer/demultiplexer
1. General description
The CBT3253A is a dual 1-of-4 high-speed TTL-compatible FET
multiplexer/demultiplexer. The low ON-resistance of the switch allows inputs to be
connected to outputs without adding propagation delay or generating additional ground
bounce noise.
1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.
The CBT3253A is characterized for operation from 40 C to +85 C.
2. Features and benefits
5  switch connection between two ports TTL-compatible input levels Minimal propagation delay through the switch Latch-up protection exceeds 100 mA per JEDEC standard JESD78 class II level A ESD protection: HBM JESD22-A114E exceeds 2000V MM JESD22-A115-A exceeds 200V CDM JESD22-C101C exceeds 1000V Multiple package options Specified from 40 Cto+85C
3. Ordering information

[1] Also known as QSOP16.
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
Rev. 3 — 24 September 2013 Product data sheet
Table 1. Ordering information

CBT3253AD 40 Cto+85C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
CBT3253ADB 40 Cto+85C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
CBT3253ADS 40 Cto+85C SSOP16[1] plastic shrink small outline package; 16 leads;
body width 3.9 mm; lead pitch 0.635 mm
SOT519-1
CBT3253APW 40 Cto+85C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NXP Semiconductors CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
4. Functional diagram

NXP Semiconductors CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
5. Pinning information
5.1 Pinning

5.2 Pin description

Table 2. Pin description

1OE, 2OE 1, 15 output enable (active LOW)
S1, S0 2, 14 select control input
1B4, 1B3, 1B2, 1B1 3, 4, 5, 6 1B outputs/inputs 7 1A input/output
GND 8 ground (0V) 9 2A input/output
2B1, 2B2, 2B3, 2B4 10, 11, 12, 13 2B outputs/inputs
VCC 16 positive supply voltage
NXP Semiconductors CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
6. Functional description

7. Limiting values

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 70 C.
8. Recommended operating conditions

Table 3. Function selection
= HIGH voltage level; L= LOW voltage level; X= Don’t care. H X X disconnect 1A and 2A X X X disconnect 1A and 2A L L L 1A to 1B1 and 2A to 2B1 L L H 1A to 1B2 and 2A to 2B2 L H L 1A to 1B3 and 2A to 2B3 L H H 1A to 1B4 and 2A to 2B4
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage 0.5 +7.0 V input voltage [1] 0.5 +7.0 V
ISW switch current continuous current through each switch - 128 mA
IIK input clamping current VI <0V 50  mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +85 C
SO16 package [2] -500 mW
SSOP16 package [3] -500 mW
TSSOP16 package [3] -500 mW
Table 5. Operating conditions

All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.
VCC supply voltage 4.5 5.5 V
VIH HIGH-level input voltage 2.0 - V
VIL LOW-level input voltage - 0.8 V
Tamb ambient temperature operating in free-air 40 +85 C
NXP Semiconductors CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
9. Static characteristics

[1] All typical values are measured at VCC =5V; Tamb =25C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3] Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. The lowest voltage of the
two (A or B) terminals determines the ON resistance.
10. Dynamic characteristics

[1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON
resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).
[2] tPLH and tPHL are the same as tpd.
tPZL and tPZH are the same as ten.
tPLZ and tPHZ are the same as tdis.
Table 6. Static characteristics

Tamb= 40 Cto+85 C.
VIK input clamping voltage VCC =4.5 V; II= 18 mA - - 1.2 V
Vpass pass voltage VI =VCC= 5.0 V; IO= 100A 3.6 3.9 4.2 V input leakage current VCC =5.5 V; VI= GND or 5.5V - - 1 A
ICC supply current VCC =5.5 V; IO =0mA; =VCCor GND 3 A
ICC additional supply current per input; VCC= 5.5 V; one input at
3.4 V, other inputs at VCC or GND
[2] -- 2.5 mA input capacitance control pins; VI=3 V or 0V -4.5 -pF
Cio(off) off-state input/output capacitance A port; VO=3 V or 0 V; nOE =VCC - 11.4 - pF
B port; VO=3 V or 0 V; nOE =VCC -3.8 -pF
Cio(on) on-state input/output capacitance A port and B port - 18.6 - pF
RON ON resistance VCC =4.5V [3] =0V; II =64mA - 5 7  =0V; II =30mA - 5 7 = 2.4 V; II =15mA - 10 15 
Table 7. Dynamic characteristics

Tamb= 40 Cto+85 C; VCC= 4.5 V to 5.5 V; for test circuit, see Figure6.
tpd propagation delay nA to nBn or nBn to nA; see Figure4 [1][2] -0.25 ns
Sn to nA; see Figure4 [1][2] 1.2 6.2 ns
ten enable time nOE to nA or nBn; see Figure5 [2] 1.3 6.3 ns
Sn to nBn; see Figure5 [2] 1.4 6.4 ns
tdis disable time nOE to nA or nBn; see Figure5 [2] 1.1 7.2 ns
Sn to nBn; see Figure5 [2] 1.0 7 ns
NXP Semiconductors CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
11. AC waveforms

Table 8. Measurement points

4.5 V to 5.5 V GND to 3.0 V 1.5 V 1.5 V VOL + 0.3 V VOH  0.3 V
NXP Semiconductors CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
12. Test information

Table 9. Test data

4.5 V to 5.5 V GND to 3.0 V  2.5 ns 50 pF 500  open 7.0 V open
NXP Semiconductors CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
13. Package outline

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