BUK9675-55A Fast Delivery |IC PHOENIX CO.,LIMITED

BUK9675-55A ,TrenchMOS(tm) transistor Logic level FETLIMITING VALUESYMBOL PARAMETER CONDITIONS MIN. MAX. UNITV Electrostatic discharge capacitor Human b ..
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BUK9675-55A
TrenchMOS(tm) transistor Logic level FET
Philips Semiconductors Product specification
TrenchMOS transistor BUK9675-55
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistorina
plastic envelope suitable for surface VDS Drain-source voltage 55 V
mounting. Using ’trench’ technology ID Drain current (DC) 19.7 A
the device features very low on-state Ptot Total power dissipation 61 W
resistance and has integral zener Tj Junction temperature 175 ˚C
diodes giving ESD protection upto RDS(ON) Drain-source on-state 75 mΩ
2kV. It is intended for use in resistance VGS = 5 V
automotive and general purpose
switching applications.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION gate drain source drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Drain-source voltage - - 55 V
VDGR Drain-gate voltage RGS = 20 kΩ -55 V
±VGS Gate-source voltage - - 10 V Drain current (DC) Tmb = 25 ˚C - 19.7 A Drain current (DC) Tmb = 100 ˚C - 13.9 A
IDM Drain current (pulse peak value) Tmb = 25 ˚C - 79 A
Ptot Total power dissipation Tmb = 25 ˚C - 61 W
Tstg, Tj Storage & operating temperature - - 55 175 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT th j-mb Thermal resistance junction to - - 2.46 K/W
mounting base
Rth j-a Thermal resistance junction to Minimum footprint, FR4 50 - K/W13
Philips Semiconductors Product specification
TrenchMOS transistor BUK9675-55
Logic level FET
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V
Tj = 175˚C 0.5 - - V
Tj = -55˚C - - 2.3
IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 μA
Tj = 175˚C - - 500 μA
IGSS Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 μA
Tj = 175˚C - 10 μA
±V(BR)GSS Gate-source breakdown IG = ±1 mA; 10 - - V
voltage
RDS(ON) Drain-source on-state VGS = 5 V; ID = 10 A - 60 75 mΩ
resistance Tj = 175˚C - - 157 mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
gfs Forward transconductance VDS = 25 V; ID = 10 A 5 - - S
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 500 650 pF
Coss Output capacitance - 110 135 pF
Crss Feedback capacitance - 60 85 pF
td on Turn-on delay time VDD = 30 V; ID = 10 A; - 10 15 ns Turn-on rise time VGS = 5 V; RG = 10 Ω - 4770ns
td off Turn-off delay time Resistive load - 28 40 ns Turn-off fall time - 33 45 ns Internal drain inductance Measured from upper edge of drain - 2.5 - nH
tab to centre of die Internal source inductance Measured from source lead - 7.5 - nH
soldering point to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain - - 19.7 A
current
IDRM Pulsed reverse drain current - - 79 A
VSD Diode forward voltage IF = 19.7 A; VGS = 0 V - 0.95 1.2 V
trr Reverse recovery time IF = 19.7 A; -dIF/dt = 100 A/μs; - 32 - ns
Qrr Reverse recovery charge VGS = -10 V; VR = 30 V - 0.12 - μC
Philips Semiconductors Product specification
TrenchMOS transistor BUK9675-55
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
WDSS Drain-source non-repetitive ID = 10 A; VDD ≤ 25 V; - - 30 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T 20 40 60 80 100 120 140 160 180
Tmb / C
PD% Normalised Power Derating120
110
100
90
80
70
60
50
40
30
20
10 10 1001
VDS/V
ID/A 20 40 60 80 100 120 140 160 180
Tmb / C
ID% Normalised Current Derating120
110
100
90
80
70
60
50
40
30
20
10
1.0E-06 0.0001 0.01 1 1000.01
0.1 Zth/ (K/W)
t/s
Philips Semiconductors Product specification
TrenchMOS transistor BUK9675-55
Logic level FET
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Fig.7. Typical transfer characteristics.
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 5 V
Fig.10. Gate threshold voltage. 246 8 100
ID/A
VDS/V
6.0 5 10 15 20 255 Transconductance, gfs (S)
Drain current, ID (A) 10 15202555 RDS(ON)/mOhm
ID/A
-100 -50 0 50 100 150 200
Tmb / degC
Rds(on) normlised to 25degCa
ID/A
VGS/V
-100 -50 0 50 100 150 2000
Tj / C
Philips Semiconductors Product specification
TrenchMOS transistor BUK9675-55
Logic level FET
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 17 A
Fig.16. Avalanche energy test circuit. 0.5 1 1.5 2 2.5 31E-05
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction 0.5 1 1.50
IF/A
VSDS/V
Ciss
Coss
Crss
Thousands pF
VDS/V0.01 0.1 1 10 100 40 60 80 100 120 140 160 180
Tmb / C
120
110
100
90
80
70
60
50
40
30
20
10
WDSS%
02468 10 120
VGS/V
QG/nC
T.U.T.
VDD
VGS=0.5 ⋅LI⋅BV /(BV −V)
Philips Semiconductors Product specification
TrenchMOS transistor BUK9675-55
Logic level FET
Fig.17. Switching test circuit.
VDDVGS

Partno	Mfg	Dc	Qty	Available	Descript
BUK9675-55A \|BUK967555A	PHILIPS	N/a	4000	avai	TrenchMOS(tm) transistor Logic level FET