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BSH105
N-channel enhancement mode MOS transistor
Philips Semiconductors Product specification
N-channel enhancement mode BSH105
MOS transistor
FEATURES SYMBOL QUICK REFERENCE DATA• Very low threshold voltage VDS = 20 V
• Fast switching
• Logic level compatible ID = 1.05 A
• Subminiature surface mount
package RDS(ON) ≤ 250 mΩ (VGS = 2.5 V)
VGS(TO) ≥ 0.4 V
GENERAL DESCRIPTION PINNING SOT23N-channel, enhancement mode,
PIN DESCRIPTIONlogic level, field-effect power
transistor. This device has very low 1 gate
threshold voltage and extremely
fast switching makingit ideal for 2 source
battery powered applications and
high speed digital interfacing. 3 drain
The BSH105is suppliedin the
SOT23 subminiature surface
mounting package.
LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNITVDS Drain-source voltage - 20 V
VDGR Drain-gate voltage RGS = 20 kΩ -20 V
VGS Gate-source voltage - ± 8V Drain current (DC) Ta = 25 ˚C - 1.05 A
Ta = 100 ˚C - 0.67 A
IDM Drain current (pulse peak value) Ta = 25 ˚C - 4.2 A
Ptot Total power dissipation Ta = 25 ˚C - 0.417 W
Ta = 100 ˚C - 0.17 W
Tstg, Tj Storage & operating temperature - 55 150 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNITRth j-a Thermal resistance junction to FR4 board, minimum 300 - K/W
ambient footprint
2
Philips Semiconductors Product specification
N-channel enhancement mode BSH105
MOS transistor
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 10 μA20 - - V
voltage
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 0.4 0.57 - V
Tj = 150˚C 0.1 - - V
RDS(ON) Drain-source on-state VGS = 4.5 V; ID = 0.6 A - 140 200 mΩ
resistance VGS = 2.5 V; ID = 0.6 A - 180 250 mΩ
VGS = 1.8 V; ID = 0.3 A - 240 300 mΩ
VGS = 2.5 V; ID = 0.6 A; Tj = 150˚C - 270 375 mΩ
gfs Forward transconductance VDS = 16 V; ID = 0.6 A 0.5 1.6 - S
IGSS Gate source leakage current VGS = ±8 V; VDS = 0 V - 10 100 nA
IDSS Zero gate voltage drain VDS = 16 V; VGS = 0 V; - 50 100 nA
current Tj = 150˚C - 1.3 10 μA
Qg(tot) Total gate charge ID = 1 A; VDD = 20 V; VGS = 4.5 V - 3.9 - nC
Qgs Gate-source charge - 0.4 - nC
Qgd Gate-drain (Miller) charge - 1.4 - nC
td on Turn-on delay time VDD = 20 V; ID = 1 A; - 2 - ns Turn-on rise time VGS = 8 V; RG = 6 Ω - 4.5 - ns
td off Turn-off delay time Resistive load - 45 - ns Turn-off fall time - 20 - nsiss Input capacitance VGS = 0 V; VDS = 16 V; f = 1 MHz - 152 - pFoss Output capacitance - 71 - pF
Crss Feedback capacitance - 33 - pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDR Continuous reverse drain Ta = 25 ˚C - - 1.05 A
current
IDRM Pulsed reverse drain current - - 4.2 A
VSD Diode forward voltage IF = 0.5 A; VGS = 0 V - 0.74 1 V
trr Reverse recovery time IF = 0.5 A; -dIF/dt = 100 A/μs; - 27 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 16 V - 19 - nC
Philips Semiconductors Product specification
N-channel enhancement mode BSH105
MOS transistor
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Ta)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Ta); conditions: VGS ≥ 4.5 V
Fig.3. Safe operating area. Ta = 25 ˚C
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
Normalised Power Dissipation, PD (%)
120 25 50 75 100 125 150
Ambient Temperature, Ta (C)
BSH105
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Peak Pulsed Drain Current, IDM (A)
Normalised Drain Current, ID (%)
120 25 50 75 100 125 150
Ambient Temperature, Ta (C)
BSH105
4.5 0.5 1 1.5 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
BSH105
Peak Pulsed Drain Current, IDM (A)
0.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5Drain Current, ID (A)
Philips Semiconductors Product specification
N-channel enhancement mode BSH105
MOS transistor
Fig.7. Typical transfer characteristics.
ID = f(VGS)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID)
Fig.9. Normalised drain-source on-state resistance.
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C
Fig.12. Typical capacitances, Ciss, Coss, Crss.
BSH105
2.5 0.5 1 1.5 2 2.5 3
Gate-Source Voltage, VGS (V)
Drain Current, ID (A) Threshold Voltage, VGS(to), (V)
0.9 25 50 75 100 125 150
Junction Temperature, Tj (C)
BSH105
3.5 0.5 1 1.5 2 2.5 3
Drain Current, ID (A)
Transconductance, gfs (S)
BSH105
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00 0.2 0.4 0.6 0.8 1
Gate-Source Voltage, VGS (V)
Drain Current, ID (A)
Normalised Drain-Source On Resistance
1.8 25 50 75 100 125 150
Junction Temperature, Tj (C)
BSH105
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Philips Semiconductors Product specification
N-channel enhancement mode BSH105
MOS transistor
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG)
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
BSH105 468
Gate charge, QG (nC)
Gate-source voltage, VGS (V) BSH105-5
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Philips Semiconductors Product specification
N-channel enhancement mode BSH105
MOS transistor
MECHANICAL DATA
Fig.15. SOT23 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
Plastic surface mounted package; 3 leads SOT23
