ADV7189KST ,High Performance 12-bit Video Decoder with Noise Shaped Video® ADCsSpecifications . 8 SDP Comb Filters........ 37 Timing Diagrams.. 9 SDP AV Code Insertion and Contro ..
ADV7190 ,6- x 10-bit 54 MHz DAC Video Encoder with Macrovision?Copy ProtectionFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17BOARD DESIGN AND LAYOUTBrightness Detect . . . ..
ADV7190KST ,Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC OutputsSPECIFICATIONSREGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 28Static Performance 5 ..
ADV7191KST ,Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC OutputsFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17APPENDIX 2BRIGHTNESS DETECT . . . . . . . . . ..
ADV7192KST ,Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan InputsFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17BRIGHTNESS DETECT REGISTER . . . . . . . . . . ..
ADV7192KSTZ ,Video Encoder with Six 10-bit DACs, 54 MHz Oversampling and ProgressiveFEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17DNR BIT DESCRIPTIONS . . . . . . . . . . . . . ..
AM27C64-70DC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-70DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-70DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-90DC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-90DE , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-90DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
ADV7189KST
High Performance 12-bit Video Decoder with Noise Shaped Video® ADCs
Multiformat SDTV Video DecoderRev. A
FEATURES
Multiformat video decoder supports NTSC-(M,N, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, Noise Shaped Video®, 12-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock compatible (LLC)
Adaptive-Digital-Line-Length-Tracking (ADLLT™)
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats:
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
12 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit/10-bit/16-bit/20-bit):
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.4% typ
Differential phase: 0.4° typ
Programmable video controls:
Peak-white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free run mode (generates stable video ouput with no I/P)
VBI decode support for
Close captioning, WSS, CGMS, EDTV, Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C® compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
80-lead LQFP Pb-free package
APPLICATIONS
High end DVD recorders
Video projectors
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Professional video products
AVR receiver
GENERAL DESCRIPTION The ADV7189 integrated video decoder automatically detects
and converts a standard analog baseband television signal
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data compatible with 20-/16-/10-/
8-bit CCIR601/CCIR656.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in line-
locked clock based systems. This makes the device ideally suited
for a broad range of applications with diverse analog video
characteristics, including tape based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The 12-bit accurate A/D conversion provides professional
quality video performance and is unmatched. This allows true
10-bit resolution in the 10-bit output mode.
The 12 analog input channels accept standard Composite, S-
Video, YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V up to 1.6 V.
Alternatively, these can be bypassed for manual settings.
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7189 modes
are set up over a 2-wire, serial, bidirectional port (I2C
compatible).
The ADV7189 is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7189 is packaged in a small 80-lead LQFP Pb-free
package.
TABLE OF CONTENTS Introduction......................................................................................4
Analog Front End.........................................................................4
Standard Definition Processor...................................................4
Functional Block Diagram..............................................................5
Specifications.....................................................................................6
Electrical Characteristics.............................................................6
Video Specifications.....................................................................7
Timing Specifications..................................................................8
Analog Specifications...................................................................8
Thermal Specifications................................................................8
Timing Diagrams..........................................................................9
Absolute Maximum Ratings..........................................................10
ESD Caution................................................................................10
Pin Configuration and Function Descriptions...........................11
Analog Front End...........................................................................13
Analog Input Muxing................................................................13
Global Control Registers...............................................................16
Power-Save Modes......................................................................16
Reset Control..............................................................................16
Global Pin Control.....................................................................17
Global Status Registers...................................................................19
Identification...............................................................................19
Status 1.........................................................................................19
Status 2.........................................................................................20
Status 3.........................................................................................20
Standard Definition Processor (SDP)..........................................21
SD Luma Path.............................................................................21
SD Chroma Path.........................................................................21
SDP Sync Processing..................................................................22
SDP VBI Data Recovery............................................................22
SDP General Setup.....................................................................22
SDP Color Controls...................................................................25
SDP Clamp Operation...............................................................27
SDP Luma Filter.........................................................................28
SDP Chroma Filter.....................................................................31
SDP Gain Operation..................................................................32
SDP Chroma Transient Improvement (CTI)..........................36
SDP Digital Noise Reduction (DNR)......................................37
SDP Comb Filters.......................................................................37
SDP AV Code Insertion and Controls.....................................40
SDP Synchronization Output Signals......................................42
SDP Sync Processing..................................................................51
SDP VBI Data Decode...............................................................52
Pixel Port Configuration...............................................................63
MPU Port Description...................................................................64
Register Accesses........................................................................65
Register Programming...............................................................65 2C Sequencer..............................................................................65 2C Control Register Map..........................................................66 2C Register Map Details...........................................................70
Appendix A......................................................................................97 2C Programming Examples.....................................................97
Appendix B....................................................................................100
PCB Layout Recommendations.............................................100
Appendix C...................................................................................102
Typical Circuit Connection....................................................102
Outline Dimensions.....................................................................104
Ordering Guide........................................................................104
REVISION HISTORY
Revision A 6/04—Changed from Rev. 0 to Rev. A.
Addition to Applications List...........................................................1
Change to Electrical Characteristics...............................................6
Changes to Table 3............................................................................8
Changes to Table 5............................................................................8
Change to Drive Strength Selection (Data) Section...................17
Changes to Figure 42....................................................................103
Revision 0 5/04—Revision 0: Initial Version
INTRODUCTION The ADV7189 is a high quality, single chip, multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-Video, and
component video into a digital ITU-R BT.656 format.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in line-
locked clock based systems. This makes the device ideally suited
for a broad range of applications with diverse analog video
characteristics, including tape based sources, broadcast sources,
security/surveillance cameras, and professional systems.
ANALOG FRONT END The ADV7189 analog front end comprises three 12-bit Noise
Shaped Video ADCs that digitize the analog video signal before
applying it to the standard definition processor. The analog
front end employs differential channels to each ADC to ensure
high performance in mixed signal applications.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7189. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping within the ADV7189. The
ADCs are configured to run in 4× oversampling mode.
STANDARD DEFINITION PROCESSOR The ADV7189 is capable of decoding a large selection of
baseband video signals in composite, S-Video, and component
formats. The video standards supported by the SDP include
PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J,
NTSC 4.43, and SECAM B/D/G/K/L. The ADV7189 can
automatically detect the video standard and process it
accordingly.
The ADV7189 has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
Video user controls such as brightness, contrast, saturation, and
hue are also available within the ADV7189.
The ADV7189 implements a patented adaptive-digital-line-
length-tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7189 to track and decode poor quality video sources such
as VCRs, noisy sources from tuner outputs, VCD players, and
camcorders. The ADV7189 contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
The SDP can process a variety of VBI data services, such as
closed captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), EDTV, Gemstar
1×/2×, and extended data service (XDS). The ADV7189 is fully
Macrovision certified; detection circuitry enables Type I, II, and
III protection levels to be identified and reported to the user.
The decoder is also fully robust to all Macrovision signal inputs.
FUNCTIONAL BLOCK DIAGRAM
–AIN1
ALS
CONTROLAND DATAS
CLK CONTROL
PIXELDATAFIELDLLC1LLC2SFL
VID
YPrPb04819-0-001
