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AM27C64-255DC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-255DC , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
AM27C64-255DI , 64 Kilobit (8 K x 8-Bit) CMOS EPROM
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ADV7181B-ADV7181BBCPZ-ADV7181BBSTZ
NTSC/PAL/SECAM Video Decoder
Multiformat SDTV Video Decoder Rev. 0
FEATURES
Multiformat video decoder supports NTSC-(M, J, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
Adaptive Digital Line Length Tracking (ADLLT™), signal
processing, and enhanced FIFO management give mini
TBC functionality
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats:
CVBS (composite video)
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit):
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
Differential phase: 0.6° typ
Programmable video controls:
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video ouput with no I/P)
VBI decode support for close captioning, WSS, CGMS, EDTV,
Gemstar® 1×/2×
Power-down mode
2-wire serial MPU interface (I2C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade:–40°C to +85°C
80-lead LQFP Pb-free package
APPLICATIONS
DVD recorders
PC Video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receiver
GENERAL DESCRIPTION The ADV7181B integrated video decoder automatically detects
and converts a standard analog baseband television signal-
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data-compatible with 16-/8-bit
CCIR601/CCIR656.
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in line-
locked clock-based systems. This makes the device ideally
suited for a broad range of applications with diverse analog
video characteristics, including tape based sources, broadcast
sources, security/surveillance cameras, and professional
systems.
The 6 analog input channels accept standard Composite,
S-Video, YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively,
these can be bypassed for manual settings.
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with ±5% line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181B modes
are set up over a 2-wire, serial, bidirectional port (I2C-
compatible).
The ADV7181B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The ADV7181B is packaged in a small 80-lead LQFP Pb-free
package.
TABLE OF CONTENTS Introduction......................................................................................3
Analog Front End.........................................................................3
Standard Definition Processor...................................................3
Functional Block Diagram..............................................................4
Specifications.....................................................................................5
Electrical Characteristics.............................................................5
Video Specifications.....................................................................6
Timing Specifications..................................................................7
Analog Specifications...................................................................7
Thermal Specifications................................................................8
Timing Diagrams..........................................................................8
Absolute Maximum Ratings............................................................9
ESD Caution..................................................................................9
Pin Configuration and Function Descriptions...........................10
Analog Front End...........................................................................12
Analog Input Muxing................................................................12
Global Control Registers...............................................................14
Power-Save Modes......................................................................14
Reset Control..............................................................................14
Global Pin Control.....................................................................15
Global Status Registers...................................................................17
Identification...............................................................................17
Status 1.........................................................................................17
Autodetection Result..................................................................17
Status 2.........................................................................................17
Status 3.........................................................................................18
Standard Definition Processor (SDP)..........................................19
SD Luma Path.............................................................................19
SD Chroma Path.........................................................................19
Sync Processing...........................................................................20
VBI Data Recovery.....................................................................20
General Setup..............................................................................20
Color Controls............................................................................22
Clamp Operation........................................................................24
Luma Filter..................................................................................25
Chroma Filter..............................................................................28
Gain Operation...........................................................................29
Chroma Transient Improvement (CTI)..................................32
Digital Noise Reduction (DNR)...............................................33
Comb Filters................................................................................34
AV Code Insertion and Controls.............................................36
Synchronization Output Signals...............................................38
Sync Processing..........................................................................45
VBI Data Decode.......................................................................46
Pixel Port Configuration...............................................................58
MPU Port Description...................................................................59
Register Accesses........................................................................60
Register Programming...............................................................60 2C Sequencer..............................................................................60 2C Register Maps...........................................................................61 2C Register Map Details...........................................................66 2C Programming Examples..........................................................88
Mode 1 CVBS Input (Composite Video on AIN6)................88
Mode 2 S-Video Input (Y on AIN1 and C on AIN4)............88
Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN3, and
Pb on AIN5)................................................................................89
Mode 4 CVBS Tuner Input CVBS PAL on AIN6...................89
PCB Layout Recommendations....................................................90
Analog Interface Inputs.............................................................90
Power Supply Decoupling.........................................................90
PLL...............................................................................................90
Digital Outputs (Both Data and Clocks).................................90
Digital Inputs..............................................................................91
Antialiasing Filters.....................................................................91
Typical Circuit Connection...........................................................92
Outline Dimensions.......................................................................94
Ordering Guide..........................................................................95
REVISION HISTORY
7/04—Revision 0: Initial Version INTRODUCTION The ADV7181B is a high quality, single chip, multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-Video, and
component video into a digital ITU-R BT.656 format.
The advanced and highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape based sources, broadcast sources,
security/surveillance cameras, and professional systems.
ANALOG FRONT END The ADV7181B analog front end comprises three 9-bit ADCs
that digitize the analog video signal before applying it to the
standard definition processor. The analog front end employs
differential channels to each ADC to ensure high performance
in mixed-signal applications.
The front end also includes a 6-channel input mux that enables
multiple video signals to be applied to the ADV7181B. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping within the ADV7181B.
The ADCs are configured to run in 4× oversampling mode.
STANDARD DEFINITION PROCESSOR The ADV7181B is capable of decoding a large selection of
baseband video signals in composite, S-Video, and component
formats. The video standards supported by the ADV7181B
include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC
M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7181B can
automatically detect the video standard and process it
accordingly.
The ADV7181B has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
Video user controls such as brightness, contrast, saturation, and
hue are also available within the ADV7181B.
The ADV7181B implements a patented adaptive digital line-
length tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7181B to track and decode poor quality video sources such
as VCRs, noisy sources from tuner outputs, VCD players, and
camcorders. The ADV7181B contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
The ADV7181B can process a variety of VBI data services such
as closed captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), EDTV, Gemstar
1×/2×, and extended data service (XDS). The ADV7181B is
fully Macrovision certified; detection circuitry enables Type I,
II, and III protection levels to be identified and reported to the
user. The decoder is also fully robust to all Macrovision signal
inputs.
FUNCTIONAL BLOCK DIAGRAM
IN6
ALS
PIXELDATAFIELDLLCSFL
VID
YPrPbINTRQ
SPECIFICATIONS Temperature range: TMIN to TMAX, –40°C to +85°C. The min/max specifications are guaranteed over this range.
ELECTRICAL CHARACTERISTICS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless
otherwise noted).
Table 1. 1 Guaranteed by characterization. ADC1 and ADC2 powered down.
3 All three ADCs powered on.
