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ADS62P45IRGCTTIN/a1avaiDual 14-bit 125MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85


ADS62P45IRGCT ,Dual 14-bit 125MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85FEATURES• Medical Imaging• Radar Systems• Maximum Sample Rate: 125 MSPS• Test and Measurement Instr ..
ADS62P48IRGCR ,Dual Channel 14 Bit, 210 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85(1)PACKAGE/ORDERING INFORMATIONSPECIFIEDPACKAGE- PACKAGE ECO LEAD/BALL PACKAGE ORDERING TRANSPORTPR ..
ADS62P48IRGCT ,Dual Channel 14 Bit, 210 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85FEATURES • Supports Input Clock Amplitude Down to 400mV Differential• Maximum Sample Rate: 250 MSPS ..
ADS62P48IRGCT ,Dual Channel 14 Bit, 210 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)VALUE UNITSupply v ..
ADS62P49IRGCR ,Dual Channel 14 Bit, 250 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85FEATURES • Supports Input Clock Amplitude Down to 400mV Differential• Maximum Sample Rate: 250 MSPS ..
ADS62P49IRGCT ,Dual Channel 14 Bit, 250 MSPS ADC with DDR LVDS & Parallel CMOS outputs 64-VQFN -40 to 85MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)VALUE UNITSupply v ..
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ADS62P45IRGCT
Dual 14-bit 125MSPS ADC with selectable DDR LVDS or CMOS outputs
ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com
SLAS561C –JULY 2007–REVISED FEBRUARY 2012
DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
Checkfor Samples: ADS62P45, ADS62P44, ADS62P43, ADS62P42
1FEATURES
Medical Imaging Radar Systems Maximum Sample Rate: 125 MSPS Test and Measurement Instrumentation 14-Bit Resolution with No Missing Codes 95 dB Crosstalk DESCRIPTION Parallel CMOS and DDR LVDS Output Options ADS62P4Xisa dual channel 14-bit A/D converter• 3.5 dB Coarse Gain and Programmable Fine family with maximum sample rates upto 125 MSPS.Gain upto6 dB for SNR/SFDR Trade-Off It combines high performance and low power
consumptionina compact 64 QFN package. Using• Digital Processing Block with: internal sample and hold and low jitter clock– Offset Correction buffer, the ADC supports high SNR and high SFDRat– Fine Gain Correction,in Stepsof 0.05 dB high input frequencies.It has coarse and fine gain
options that can be used to improve SFDR– Decimation by 2/4/8
performanceat lower full-scale input ranges.– Built-in and Custom Programmable 24-Tap
Low-/High-/Band-Pass Filters
ADS62P4X includesa digital processing block that
consistsof several useful and commonly used digital• Supports Sine, LVPECL, LVDS and LVCMOS functions such as ADC offset correction, fine gainClocks and Amplitude Downto 400 mVPP correction (in stepsof 0.05 dB), decimation by 2,4,8• Clock Duty Cycle Stabilizer and in-built and custom programmable filters. By Internal Reference; Supports External default, the digital processing blockis bypassed, and
Reference also
its functions are disabled. 64-QFN Package (9mm× 9mm) Two output interface options exist– parallel CMOS
and DDR LVDS (Double Data Rate). ADS62P4X• Pin Compatible 12-Bit Family (ADS62P2X)
includes internal references while traditional
reference pins and associated decoupling capacitorsAPPLICATIONS have been eliminated. Nevertheless, the device can• Wireless Communications Infrastructure alsobe driven with an external reference. The device specified over the industrial temperature range• Software Defined Radio
(–40°Cto 85°C).• Power Amplifier Linearization 802.16d/e
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