ADP3310AR-2.8-ADP3310AR-3.3 Fast Delivery |IC PHOENIX CO.,LIMITED

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ADP3310AR-2.8-ADP3310AR-3.3
OutputV: 2.8V; precision voltage regulator controller. For desktop computers, handheld instruments
REV.A
Precision Voltage
Regulator Controller
FUNCTIONAL BLOCK DIAGRAM
Figure 1.Typical Application Circuit
FEATURES
61.5% Accuracy Over Line, Load and Temperature
Low 800 mA (Typical) Quiescent Current
Shutdown Current: 1 mA (Typical)
Stable with 10 mF Load Capacitor
+2.5 V to +15 V Operating Range
Fixed Output Voltage Options: 2.8 V, 3 V, 3.3 V, 5 V
Up to 10 A Output Current
SO-8 Package
–408C to +858C Ambient Temperature Range
Internal Gate to Source Protective Clamp
Current and Thermal Limiting
Programmable Current Limit
Foldback Current Limit
APPLICATIONS
Desktop Computers
Handheld Instruments
Cellular Telephones
Battery Operated Devices
Solar Powered Instruments
High Efficiency Linear Power Supplies
Battery Chargers
GENERAL DESCRIPTION
The ADP3310 is a precision voltage regulator controller that
can be used with an external Power PMOS device such as the
NDP6020P to form a two chip low dropout linear regulator.
The low quiescent current (800 mA) and the Enable feature
make this device especially suitable for battery powered systems.
The dropout voltage at 1 A is only 70 mV when used with the
NDP6020P, allowing operation with minimal headroom and
prolonging battery useful life. The ADP3310 can drive a wide
range of currents, depending on the external PMOS device used.
Additional features of this device include: high accuracy (–1.5%)
over line, load and temperature, gate-to-source voltage clamp to
protect the external MOSFET and foldback current limit. A
current limit threshold voltage of 50 mV (typ) allows 50 mW of
board metal trace resistance to provide a 1 A current limit.
The ADP3310 operates from a wide input voltage range from
2.5V to 15V and is available in a small SO-8 package.
ADP3310–SPECIFICATIONS
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Input Voltage, VIN␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 V
Enable Input Voltage . . . . . . . . . . . . . . . 0.3 V to VIN + 0.3 V
Operating Junction Temperature Range . . . –40°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°CJA (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . .+121°C/WJA (2-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . .+150°C/W
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
(VIN = VOUT + 1 V, TA = –408C to +858C unless otherwise noted)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3310 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Table I.Alternate PMOS Devices
PD @ 25°C
ORDERING GUIDE
*SO = Small Outline. Contact the factory for the availability of other output
voltage options from 5 V to 16.5 V.
Refer to the ADP3319 data sheet for 1.8 V and 2.5 V output voltage options.
Refer to the ADP3328 data sheet for adjustable output version.
PIN FUNCTION DESCRIPTIONS
2, 6
4VIN
5VOUT
PIN CONFIGURATION
SO-8
ADP3310
–Typical Performance Characteristics (Circuit of Figure 1)
ILOAD – mA
OUT
– V
3.295
Figure 2.VOUT vs. ILOAD (VIN = 5 V)
VIN – V
OUT
– V
Figure 3.VOUT vs. VIN (ILOAD = 1 A)
VIN – V
OUT
– V
3.295
Figure 4.VOUT vs. VIN (ILOAD = 10 mA)
Figure 5.IGND vs. VIN (ILOAD = 10 mA)
Figure 6.IGND vs. VIN (ILOAD = 1 A)
Figure 7.IGND vs. ILOAD (VIN = 5 V)
TEMPERATURE – 8C
GND
– mA
1.1
Figure 8.Quiescent Current vs. Temperature
VIN – V
OUT
– V
2.0
Figure 9.Power-Up/Power-Down
5ms/DIV
– V
OUT
– V
Figure 10.Line Transient Response—(10 mF Load)

Figure 11.Load Transient Response
Figure 12.Ripple Rejection
ILOAD – mA
OUT
– V
2.5
Figure 13.Foldback Current
ADP3310
APPLICATION INFORMATION
The ADP3310 is very easy to use. A P-channel power MOSFET
and a small capacitor on the output is all that is needed to form
an inexpensive ultralow dropout regulator. The advantage of
using the ADP3310 controller is that it can drive a pass PMOS
FET to provide a regulated output at high current.
FET Selection
The type and size of the pass transistor are determined by the
threshold voltage, input-output voltage differential and load
current. The selected PMOS must satisfy the physical and
thermal design requirements. Table I shows a partial list of
manufacturers providing the PMOS devices. To ensure that the
maximum VGS provided by the controller will turn on the FET
at worst case conditions (i.e., temperature and manufacturing
tolerances), the maximum available VGS must be determined.
Maximum VGS is calculated as follows:
(1)VGS = VIN – VBE – IOMAX · RS
IOMAX = Maximum Output Current
RS = Current Sense Resistor
VBE~ 0.7 V (Room Temp)
~ 0.5 V (Hot)
~ 0.9 V (Cold)
For Example: VIN = 5 V, VO = 3.3 V and IOMAX = 3 A,
VGS = 5 V – 0.7 V – 3 A · 11 mW = 4.27 V
Equation (1) applies to a gate-to-source voltage less than the
gate to source clamp voltage.
(2)VDS = VIN – VO
VDS = 5 V – 3.3 V = 1.7 V
If VIN £ 5 V, logic level FET should be considered.
If VIN > 5 V, either logic level or standard MOSFET can be used.
The difference between VIS and VOUT (VDS) must exceed the
voltage drop due to the load current and the ON resistance of
the FET. As a safety margin, it is recommended to use a MOS-
FET with a VGS at least 1.5 times lower than the calculated VGS
value from Equation 1. Also, in the event the circuit is shorted
to ground, the MOSFET must be able to conduct the maximum
short circuit current. The selected MOSFET must satisfy these
criteria; otherwise, a different pass device should be used. If the
FET data is not available in the catalogue, contact the FET
manufacturer.
Thermal Design
The maximum allowable thermal resistance between the FET
junction and the highest ambient temperature must be taken
into account to determine the type of FET package used. One
square inch of PCB copper area as heatsink yields a typicalJA ~ 60°C/W for the SOT-223 package and qJA ~ 50°C/W for
the SO-8 package. For substantially lower thermal resistances,2PAK or TO-220 type of packages are recommended.
For normal applications, the FET can be directly mounted to the
PCB. But, for higher power applications, an external heat sink is
required to satisfy the qJA requirement and provide adequate heatsink.
Calculating thermal resistance for VIN = 5 V, VO = 3.3 V, and
IO = 3 A:
VDSMAX= Maximum Drain to Source Voltage
IOMAX= Maximum Output CurrentJA=
For such a low qJA, a P-channel FET from Fairchild, such as
NDP6020P in a heatsink mountable TO-220 package, is
required. The required external heatsink is determined as
follows:CA= qJA – qJCCA= Case-to-Ambient Thermal ResistanceJA= Junction-to-Ambient Thermal ResistanceJC= Junction-to-Case Thermal ResistanceJC= 2°C/W for NDP6020PCA= 14.7°C/W – 2°C/W = 12.7°C/W
For a safety margin, select a heatsink with a qCA less than half of
the value calculated above to allow extended duration of short
circuit. In a natural convection environment, a large heatsink
such as 3" length of Type 63020 extrusion from Aavid Engineering
is required.
External Capacitors
The ADP3310 is stable with virtually any good quality capaci-
tors (anyCAP™), independent of the capacitor’s minimum ESR
(Effective Series Resistance) value. The actual value of the ca-
pacitor and its associated ESR depends on the gm and ca-
pacitance of the external PMOS device. A 10mF capacitor at the
output is sufficient to ensure stability for up to 10A output
current. Larger capacitors can be used if high output current
surges are anticipated. Extremely low ESR capacitors (ESR»0)
such as multilayer ceramic or OSCON are preferred because
they offer lower ripple on the output. For less demanding
requirements, a standard tantalum or even an aluminum
electrolytic is adequate. However, if an aluminum electrolytic is
used, be sure it meets the temperature requirements because
aluminum electrolytic has poor performance over temperature.
Shutdown Mode
Applying a TTL high signal to the EN pin or tying it to the
input pin will enable the output. Pulling this pin low or tying it
to ground will disable the output. In shutdown mode, the
controller’s quiescent current is reduced to less than 1mA.
Gate-to-Source Clamp
An 8V gate-to-source voltage clamp is provided to protect the
MOSFET in the event the output is suddenly shorted to
ground. This allows the use of the new, low on-state resistance
(RDSON) FETs.
Short Circuit Protection
The power FET is protected during short circuit conditions
with a foldback type of current limiting which significantly re-
duces the current.
Current Sense Resistor
Current limit is achieved by setting an appropriate current sense
resistor (RS) across the current limit threshold voltage. Current
limit sense resistor RS is calculated as follows:

Partno	Mfg	Dc	Qty	Available	Descript
ADP3310AR-2.8 \|ADP3310AR28	ADI	N/a	18	avai	OutputV: 2.8V; precision voltage regulator controller. For desktop computers, handheld instruments
ADP3310AR-3.3 \|ADP3310AR33	AD	N/a	8080	avai	OutputV: 3.3V; precision voltage regulator controller. For desktop computers, handheld instruments