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ADP3203
1 Or 2 Phase IMVP-III Compatible Core Controller For Latest Intel Mobile Processors
REV.0
2-Phase IMVP-II and IMVP-III
Core Controller for Mobile CPUsADOPT is a trademark of Analog Devices.
FEATURES
Pin Selectable 1- or 2-Phase Operation
Static and Dynamic Current Sharing Characteristics
Backward Compatible to IMVP-II
Superior Load Transient Response with ADOPTTM
Optimal Positioning Technology
Noise Blanking for Speed and Stability
Synchronous Rectifier Control Extends Battery Life
Smooth Output Transition During VID Code Change
Cycle-by-Cycle Current Limiting
Hiccup or Latched Overload Protection
Transient Glitch-Free Power Good
Soft Start Eliminates Power-On In-Rush Current Surge
2-Level Overvoltage and Reverse Voltage Protection
APPLICATIONS
IMVP-II and IMVP-III Core DC-to-DC Converters
Fixed Voltage Mobile CPU Core DC-to-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
FUNCTIONAL BLOCK DIAGRAM
VID0
VID1
VID2
VID3
VID4
DACOUT
GND
VCC
CS+
CS–
REG
COREFB
PWRGD
BOM
DSLP
DPRSLP
HYSSET
BSHIFT
DSHIFT
CLAMP
RAMP
DRVLSD
OUT2
OUT1
CS1
CS2
GENERAL DESCRIPTIONThe ADP3203 is a 1- or 2-phase hysteretic peak current dc-to-dc
buck converter controller dedicated to power a mobile
processor’s core. The optimized low voltage design is powered
from the 3.3 V system supply and draws only 10 µA maximum
in shutdown. The nominal output voltage is set by a 5-bit VID
code. To accommodate the transition time required by the
newest processors for on-the-fly VID changes, the ADP3203
features high speed operation to allow a minimized inductor size
that results in the fastest change of current to the output. To
further allow for the minimum number of output capacitors to
be used, the ADP3203 features active voltage positioning with
ADOPT optimal compensation to ensure a superior load transient
response. The output signal interfaces with the ADP3415
MOSFET driver that is optimized for high speed and high effi-
ciency for driving both the top and bottom MOSFETs of the buck
converter. The ADP3203 is capable of controlling the synchronous
rectifier to extend battery lifetime in light load conditions.
ADP3203–SPECIFICATIONS1VID DAC
(0�C � TA � 100�C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB =
VDAC (0 VDACOUT), VREG = VCS– = VVID = 1.25 V, ROUT1 =ROUT2
100k�, COUT1 = COUT2 = 10 pF, CSS =0.047 �F, RPWRGD = 680 � to 1.2 V, RCLAMP = 5.1 k� to VCC; HYSSET, BSHIFT, DSHIFT, and
DPRSHIFT are open; BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted.) Current sunk by a pin has a positive sign, sourced by a pin has a
negative sign. Negative sign is disregarded for min and max values.
ADP3203NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.Guaranteed by characterization.Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-Core-Good-window voltage (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) to the
COREFB pin right after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay
time. 2) PWRGD is forced to fail (VCOREFB, BAD = 1.0 V at VVID = 1.25 V setting) but gets into the Core Good window
(VCOREFB, GOOD = 1.25 V) right after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified
blanking delay time.Guaranteed by design.Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within ±1% of its steady state value.40 mVp-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.Measured between the 30% and 70% points of the output voltage swing.DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.
LOW SIDE DRIVE CONTROL
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS*Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V
All Other Inputs/Outputs . . . . . . . . . . .–0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . 0°C to 100°C
Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C
�JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
PIN CONFIGURATION
Table I. VID Code
ORDERING GUIDE
ADP3203
PIN FUNCTION DESCRIPTIONS4–8
PIN FUNCTION DESCRIPTIONS (continued)ADP3203
PIN FUNCTION DESCRIPTIONS (continued)
