ADP3163JRU-REEL ,5-Bit Programmable 2-/3-Phase Synchronous Buck ControllerSPECIFICATIONS(VCC = 12 V, I = 150 A, T = 0C to 70C, unless otherwise noted.)REF AParameter Symb ..
ADP3163JRUZ-REEL ,5-Bit Programmable 2-/3-Phase Synchronous Buck ControllerGENERAL DESCRIPTION The ADP3163 also uses a unique supplemental regulation tech-The ADP3163 is a hi ..
ADP3164JRU ,5-Bit Programmable 4-Phase Synchronous Buck ControllerSPECIFICATIONS (VCC = 12 V, I = 150 A, T = 0C to 70C, unless otherwise noted.)REF AParameter Sym ..
ADP3164JRU ,5-Bit Programmable 4-Phase Synchronous Buck ControllerGENERAL DESCRIPTION The ADP3164 also uses a unique supplemental regulation tech-The ADP3164 is a hi ..
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ADP3166JRU-REEL ,5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck ControllerGENERAL DESCRIPTIONILIMIT 15The ADP3166 is a highly efficient, multiphase, synchronous17 CSSUMCURRE ..
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ADP3163JRU-REEL-ADP3163JRUZ-REEL
5-Bit Programmable 2-/3-Phase Synchronous Buck Controller
REV.0
5-Bit Programmable 2-/3-Phase
Synchronous Buck Controller
FUNCTIONAL BLOCK DIAGRAM
CS–
CS+
COMP
PWM3
PWM1
PGND
PWM2
VID4VID3VID2VID1
VCC
REF
GND
VID0
SHARE
PWRGD
FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors
Complies with VRM 9.0 and Intel VR Down Guideline
with Lowest System Cost
Digitally Selectable 2- or 3-Phase Operation
at up to 500 kHz per Phase
Quad Logic-level PWM Outputs for Interface to
External High-Power Drivers
Active Current Balancing between All Output Phases
Accurate Multiple VRM Module Current Sharing
5-Bit Digitally Programmable 1.1 V to 1.85 V Output
Total Output Accuracy �0.8% Over Temperature
Current-Mode Operation
Short Circuit Protection
Enhanced Power Good Output Detects Open Outputs in
Multi-VRM Power Systems
Overvoltage Protection Crowbar Protects Microprocessors
with No Additional External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Pentium® 4 Processors
AMD Athlon Processors
VRM Modules
GENERAL DESCRIPTIONThe ADP3163 is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 5 V or
12 V main supply into the core supply voltage required by high
performance Intel processors. The ADP3163 uses an internal
5-bit DAC to read a voltage identification (VID) code directly
from the processor, which is used to set the output voltage between
1.1 V and 1.85 V. The ADP3163 uses a current mode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2- or 3-phase operation, allowing for
the construction of up to three complementary buck switching
stages. These stages share the dc output current to reduce
overall output voltage ripple. An active current balancing func-
tion ensures that all phases carry equal portions of the total load
current, even under large transient loads, to minimize the size of
the inductors.
The ADP3163 also uses a unique supplemental regulation tech-
nique called active voltage positioning (ADOPT) to enhance
load transient performance. Active voltage positioning results in
a dc/dc converter that meets the stringent output voltage specifi-
cations for high performance processors, with the minimum
number of output capacitors and smallest footprint. Unlike
voltage-mode and standard current-mode architectures, active
voltage positioning adjusts the output voltage as a function of
the load current so that it is always optimally positioned for a
system transient. The ADP3163 also provides accurate and
reliable short circuit protection, adjustable current limiting, and
an enhanced Power Good output that can detect open outputs
in any phase for single or multi-VRM systems.
The ADP3163 is specified over the commercial temperature
range of 0°C to 70°C and is available in a 20-lead TSSOP package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
ADP3163–SPECIFICATIONS1
(VCC = 12 V, IREF = 150 �A, TA = 0�C to 70�C, unless otherwise noted.)VID INPUTS
CURRENT SHARING
POWER GOOD COMPARATOR
ADP3163NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).Guaranteed by design, not tested in production.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC +0.3 V
All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
ORDERING GUIDE
PIN CONFIGURATION
RU-20
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3163 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ADP3163
PIN FUNCTION DESCRIPTIONSFigure 1.Closed-Loop Output Voltage Accuracy Test Circuit
Table I.PWM Outputs vs. Phase Control Code
TPC 1. Oscillator Frequency vs. Timing Capacitor (CT)
TPC 2.Supply Current vs. Oscillator Frequency
TPC 3.Output Accuracy Distribution
ADP3163
Table II.Output Voltage vs. VID Code
THEORY OF OPERATIONThe ADP3163 combines a current-mode, fixed frequency PWM
controller with multiphase logic outputs for use in a 2- or 3-phase
synchronous buck power converter. Multiphase operation is
important for switching the high currents required by high
performance microprocessors. Handling the high current in a
single-phase converter would place unreasonable requirements on
the power components such as inductor wire size and MOSFET
ON-resistance and thermal dissipation. The ADP3163’s high-side
current sensing topology ensures that the load currents are
balanced in each phase, such that no single phase has to carry
more than it’s share of the power. An additional benefit of high
side current sensing over output current sensing is that the
average current through the sense resistor is reduced by the duty
cycle of the converter allowing the use of a lower power, lower
cost resistor. The outputs of the ADP3163 are logic drivers
only and are not intended to directly drive external power
MOSFETs. Instead, the ADP3163 should be paired with driv-
ers such as the ADP3413 or ADP3414.
The frequency of the ADP3163 is set by an external capacitor
connected to the CT pin. The phase relationship and number of
phase is inherently limited to 50% for 2-phase operation and
33% for 3-phase operation. While one phase is on, all other
phases remain off. In no case can more than one output be high
at any time.
Output Voltage SensingThe output voltage is sensed at the FB pin allowing for remote
sensing. To maintain the accuracy of the remote sensing, the
GND pin should also be connected close to the load. A voltage
error amplifier (gm) amplifies the difference between the output
voltage and a programmable reference voltage. The reference
voltage is programmed between 1.1 V and 1.85 V by an internal
5-bit DAC, which reads the code at the voltage identification
(VID) pins. (Refer to Table II for the output voltage versus VID
pin code information.)
Active Voltage PositioningThe ADP3163 uses Analog Devices Optimal Positioning Tech-
nology (ADOPT), a unique supplemental regulation technique
that uses active voltage positioning and provides optimal com-
pensation for load transients. When implemented, ADOPT
adjusts the output voltage as a function of the load current, so
that it is always optimally positioned for a load transient.
Standard (passive) voltage positioning has poor dynamic perfor-
mance, rendering it ineffective under the stringent repetitive
transient conditions required by high performance processors.
ADOPT, however, provides optimal bandwidth for transient
response that yields optimal load transient response with the
minimum number of output capacitors.
Reference OutputA 3.0V reference is available on the ADP3163. This reference
is normally used to set the voltage positioning accurately using a
resistor divider to the COMP pin. In addition, the reference can
be used for other functions such as generating a regulated volt-
age with an external amplifier. The reference is bypassed with
a 1 nF capacitor to ground. It is not intended to supply large
capacitive loads, and it should not be used to provide more than
300μA of output current.
Cycle-by-Cycle OperationDuring normal operation (when the output voltage is regulated),
the voltage-error amplifier and the current comparator are the
main control elements. The voltage at the CT pin of the oscilla-
tor ramps between 0V and 3V. When that voltage reaches 3V,
the oscillator sets the driver logic, which sets PWM1 high. Dur-
ing the ON time of Phase 1, the driver IC turns on the Phase 1
high-side MOSFET. The CS+ and CS– pins monitor the current
through the sense resistor that feeds all the high side MOSFETs.
When the voltage between the two pins exceeds the threshold
level, the driver logic is reset and the PWM1 output goes low. This
signals the driver IC to turn off the Phase 1 high side MOSFET
and turn on the Phase 1 low side MOSFET. On the next cycle
of the oscillator, the driver logic toggles and sets PWM2 high.
On each following cycle of the oscillator, the driver logic cycles
between each of the active PWM outputs based on the logic
state of the PC pin. In each case, the current comparator resets
the PWM output low when its threshold is reached. As the load
current increases, the output voltage starts to decrease. This
causes an increase in the output of the gm amplifier, which in
turn leads to an increase in the current comparator threshold,
Active Current SharingThe ADP3163 ensures current balance in all the active phases
by sensing the current through a single sense resistor. During
one phase's ON time, the current through the respective high
side MOSFET and inductor is measured through the sense
resistor. When the comparator threshold is reached, the high side
MOSFET turns off. On the next cycle the ADP3163 switches to
the next phase. The current is measured with the same sense
resistor and the same internal comparator, ensuring accurate
matching. This scheme is immune to imbalances in the MOSFET’s
RDS(ON) and inductor parasitic resistance.
If for some reason one of the phases fails, the other phases will
still be limited to their maximum output current (one over the
total number phases times the total short circuit current limit).
If this is not sufficient to supply the load, the output voltage will
droop and cause the PWRGD output to signal that the output
voltage has fallen out of its specified range. If one of the phases
has an open circuit failure, the ADP3163 will detect the open
phase and signal the problem via the PWRGD pin (see Power
Good Monitoring section).
Current Sharing in Multi-VRM ApplicationsThe ADP3163 includes a SHARE pin to allow multiple VRMs
to accurately share load current. In multiple VRM applications,
the SHARE pins should be connected together. This pin is a
low impedance buffered output of the COMP pin voltage. The
output of the buffer is internally connected to set the threshold
of the current sense comparator. The buffer has a 400 μA sink
current, and a 2 mA sourcing capability. The strong pull-up
allows one VRM to control the current threshold set point for
all ADP3163s connected together. The ADP3163’s high accuracy
current set threshold ensures good current balance between
VRMs. Also, the low impedance of the buffer minimizes noise
pick up on this trace which is routed to multiple VRMs. This
circuit operates in addition to the active current sharing between
phases of each VRM described above.
Short Circuit ProtectionThe ADP3163 has multiple levels of short circuit protection to
ensure fail-safe operation. The sense resistor and the maximum
current sense threshold voltage given in the specifications set the
peak current limit.
When the load current exceeds the current limit, the excess current
discharges the output capacitor. When the output voltage is below
the foldback threshold, VFB(LOW), the maximum deliverable output
current is cut by reducing the current sense threshold from
the current limit threshold, VCS(CL), to the foldback threshold,
VCS(FOLD). Along with the resulting current foldback, the oscilla-
tor frequency is reduced by a factor of five when the output is
0 V. This further reduces the average current in short circuit.
Power Good MonitoringThe Power Good comparator monitors the output voltage of the
supply via the FB pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indicates
that the output voltage is within the specified range of the nomi-
nal output voltage requested by the VID DAC. PWRGD will go
low if the output is outside this range.
Short circuits in a VRM power path are relatively easy to detect
voltage specification even when one VRM is not functioning.
The ADP3163 addresses this problem by monitoring both the
output voltage and the switch current to determine the state of
the PWRGD output.
The output voltage portion of the Power Good monitor domi-
nates; as long as the output voltage is outside the specified
window, PWRGD will remain low. If the output voltage is
within specification, a second circuit checks to make sure that
current is being delivered to the output by each phase. If no
current is detected in a phase for three consecutive cycles, it is
assumed that an open circuit exists somewhere in the power
path, and PWRGD will be pulled low.
Output CrowbarThe ADP3163 includes a crowbar comparator that senses when
the output voltage rises higher than the specified trip threshold,
VCROWBAR. This comparator overrides the control loop and sets
both PWM outputs low. The driver ICs turn off the high side
MOSFETs and turn on the low side MOSFETs, thus pulling
the output down as the reversed current builds up in the induc-
tors. If the output overvoltage is due to a short of the high side
MOSFET, this action will current limit the input supply or blow
its fuse, protecting the microprocessor from destruction. The
crowbar comparator releases when the output drops below the
specified reset threshold, and the controller returns to normal
operation if the cause of the over voltage failure does not persist.
Output DisableThe ADP3163 includes an output disable function that turns off
the control loop to bring the output voltage to 0V. Because an
extra pin is not available, the disable feature is accomplished by
pulling the COMP pin to ground. When the COMP pin drops
below 0.8V, the oscillator stops and all PWM signals are driven
low. When in this state, the reference voltage is still available.
The COMP pin should be pulled down with an open drain
structure capable of sinking at least 2 mA.
APPLICATION INFORMATIONThe design parameters for a typical Intel Pentium 4 CPU appli-
cation are as follows:
Input voltage (VIN) = 12 V
VID setting voltage (VVID) = 1.5 V
Nominal output voltage at no load (VONL) = 1.475 V
Nominal output voltage at 65 A load (VOFL) = 1.377 V
Static output voltage drop based on a 1.5 mΩ load line
(ROUT) from no load to full load (VΔ) = VONL – VOFL =
1.475 V – 1.377 V = 98 mV
Maximum Output Current (IO) = 65 A
Number of Phases (n) = 3
CT Selection—Choosing the Clock FrequencyThe ADP3163 uses a fixed-frequency control architecture. The
frequency is set by an external timing capacitor, CT. The clock
frequency and the state of the PC pin determine the switching
frequency, which relates directly to switching losses and the
sizes of the inductors and input and output capacitors. With PC
tied to REF, a clock frequency of 600 kHz sets the switching
frequency of each phase, fSW, to 200 kHz, which represents a
practical trade-off between the switching losses and the sizes of
ADP3163tolerance, e.g., an MLC capacitor with NPO dielectric and with
5% or less tolerance.
Inductance SelectionThe choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFETs, but allows using smaller-size inductors and, for
a specified peak-to-peak transient deviation, output capacitors
with less total capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses, but
requires larger-size inductors and more output capacitance for
the same peak-to-peak transient deviation. In a three-phase
converter, a practical value for the peak-to-peak inductor ripple
current is under 50% of the dc current in the same inductor. A
choice of 50% for this particular design example yields a total
peak-to-peak output ripple current of 12% of the total dc output
current. The following equation shows the relationship between
the inductance, oscillator frequency, peak-to-peak ripple current
in an inductor and input and output voltages.(1)
For an 11 A peak-to-peak ripple current, which corresponds to
50% of the 22 A full-load dc current in an inductor, Equation 1
yields an inductance of:
A 600 nH inductor can be used, which gives a calculated ripple
current of 10.9 A at no load. The inductor should not saturate
at the peak current of 27 A, and should be able to handle the
sum of the power dissipation caused by the average current of
22 A in the winding and the core loss.
The output ripple current is smaller than the inductor ripple
current due to the three phases partially canceling. This can be
calculated as follows:(2)
Designing an InductorOnce the inductance is known, the next step is either to design
an inductor or find a standard inductor that comes as close as
possible to meeting the overall design goals. The first decision in
designing the inductor is to choose the core material. There are
several possibilities for providing low core loss at high frequen-
cies. Two examples are the powder cores (e.g., Kool-Mμ® from
Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or
3F4 from Philips). Low frequency powdered iron cores should
be avoided due to their high core loss, especially when the
inductor value is relatively low and the ripple current is high.
Two main core types can be used in this application. Open
magnetic loop types, such as beads, beads on leads, and rods
the circuitry surrounding the inductor. Closed-loop types, such
as pot cores, PQ, U, and E cores, or toroids, cost more, but
have much better EMI/RFI performance. A good compromise
between price and performance are cores with a toroidal shape.
There are many useful references for quickly designing a power
inductor. Table III gives some examples.
Table III.Magnetics Design ReferencesMagnetic Designer Software
Intusoft (http://www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-DC
Converters
McLyman, Kg Magnetics
ISBN 1-883107-00-08
Selecting a Standard InductorThe companies listed in Table IV can provide design consulta-
tion and deliver power inductors optimized for high power
applications upon request.
Table IV.Power Inductor ManufacturersCoilcraft
(847)639-6400
http://www.coilcraft.com
Coiltronics
(561)752-5000
http://www.coiltronics.com
Sumida Electric Company
(408)982-9660
http://www.sumida.com
RSENSEThe value of RSENSE is based on the maximum required output
current. The current comparator of the ADP3163 has a mini-
mum current limit threshold of 143 mV. Note that the 143 mV
value cannot be used for the maximum specified nominal cur-
rent, as headroom is needed for ripple current and tolerances.
The current comparator threshold sets the peak of the inductor
current yielding a maximum output current, IO, which equals
the peak inductor current value less half of the peak-to-peak induc-
tor ripple current. From this, the maximum value of RSENSE is
calculated as:
(3)
In this case, 5 mΩ was chosen as the closest standard value.
Once RSENSE has been chosen, the output current at the point
where current limit is reached, IOUT(CL), can be calculated using
the maximum current sense threshold of 173 mV:
