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AK002M4-31 , GaAs MMIC Control FET in SOT 143 DC-2.5 GHz
ADN2850BCP25
Dual 10-Bit Programmable Non-Volatile Resistor
REV.B
Nonvolatile Memory, Dual
1024-Position Programmable Resistors
FUNCTIONAL BLOCK DIAGRAMFigure 1.RWB(D) vs. Decimal Code
FEATURES
Dual, 1024-Position Resolution
25 k�, 250 k� Full-Scale Resistance
Low Temperature Coefficient: 35 ppm/�C
Nonvolatile Memory1 Preset Maintains Wiper Settings
Permanent Memory Write-Protection
Wiper Settings Read Back
Actual Tolerance Stored in EEMEM1
Linear Increment/Decrement
Log Taper Increment/Decrement
SPI Compatible Serial Interface
3 V to 5 V Single Supply or �2.5 V Dual Supply
26 Bytes User Nonvolatile Memory for Constant Storage
Current Monitoring Configurable Function
100-Year Typical Data Retention TA = 55�C
APPLICATIONS
SONET, SDH, ATM, Gigabit Ethernet, DWDM Laser
Diode Driver Optical Supervisory Systems
GENERAL DESCRIPTIONThe ADN2850 provides dual-channel, digitally controlled program-
mable resistors2 with resolution of 1024 positions. These devices
perform the same electronic adjustment function as a mechanical
rheostat with enhanced resolution, solid-state reliability, and
superior low temperature coefficient performance. The ADN2850’s
versatile programming via a standard serial interface allowsmodes of operation and adjustment, including scratch pad pro-
gramming, memory storing and retrieving, increment/decrement,
log taper adjustment, wiper setting readback, and extra user
defined EEMEM1.
Another key feature of the ADN2850 is that the actual tolerance
is stored in the EEMEM. The actual full-scale resistance can
therefore be known, which is valuable for tolerance matching
and calibration.
In the scratch pad programming mode, a specific setting can be
programmed directly to the RDAC2 register, which sets the resis-
tance between terminals W and B. The RDAC register can also
be loaded with a value previously stored in the EEMEM register.
The value in the EEMEM can be changed or protected. When
changes are made to the RDAC register, the value of the new
setting can be saved into the EEMEM. Thereafter, such value will
be transferred automatically to the RDAC register during system
power ON, which is enabled by the internal preset strobe.
EEMEM can also be retrieved through direct programming and
external preset pin control.
The linear step increment and decrement commands enable the
setting in the RDAC register to be moved UP or DOWN, one step
at a time. For logarithmic changes in wiper setting, a left/right
bit shift command adjusts the level in ±6 dB steps.
The ADN2850 is available in the 5 mm � 5 mm 16-lead frame chip
scale LFCSP and thin 16-lead TSSOP packages. All parts are
guaranteed to operate over the extended industrial temperature
range of –40°C to +85°C.*Patent pending
NOTESThe term nonvolatile memory and EEMEM are used interchangeably.The term programmable resistor and RDAC are used interchangeably.
ADN2850–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS 25 k�, 250 k� VERSIONSDC CHARACTERISTICS RHEOSTAT MODE (Specifications apply to all RDACs)
RESISTOR TERMINALS
POWER SUPPLIES
DYNAMIC CHARACTERISTICS
(VDD = 3 V to 5.5 V and –40�C < TA < +85�C,
unless otherwise noted.)1
ADN2850INTERFACE TIMING CHARACTERISTICS (apply to all parts)
NOTESParts can be operated at 2.7 V single supply, except from 08C to –408C, where minimum 3 V is needed.Typicals represent average readings at 258C and VDD = 5 V.Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA for VDD = 2.7 V and IW ~ 400 µA for VDD = 5 V.Resistor terminals W and B have no limitations on polarity with respect to each other.Guaranteed by design and not subject to production test.Common-mode leakage current is a measure of the dc leakage from any terminal B and W to a common-mode bias level of VDD/2.Transfer (XFR) mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.PDISS is calculated from (IDD � VDD) + (ISS � VSS).9Applies to photodiode of optical receiver.All dynamic characteristics use VDD = +2.5 V and VSS = –2.5 V.See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5V.
Switching characteristics are measured using both VDD = 3 V and 5 V.Propagation delay depends on value of VDD, RPULL_UP, and CL. See Applications section.Valid for commands that do not activate the RDY pin.RDY pin low only for commands 2, 3, 8, 9, 10, and PR hardware pulse: CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.1 ms; CMD_2, 3 ~ 20 ms. Device operation atTA=–40°C
and VDD < 3 V extends the save time to 35 ms.Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 Vwill
derate with junction temperature.
Specifications subject to change without notice.
The ADN2850 contains 16,000 transistors. Die size: 93 mil � 103 mil, 10,197 sq mil.
ADN2850
TIMING DIAGRAMSFigure 2a. CPHA = 1 Timing Diagram
Figure 2b.CPHA = 0 Timing Diagram
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
VB, VW to GND . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
IB, IW
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Digital Inputs and Output Voltage
to GND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Operating Temperature Range3 . . . . . . . . . . .–40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering4
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215�C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .220�C
Thermal Resistance Junction-to-Ambient θJA,
LFCSP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
Thermal Resistance Junction-to-Case θJC,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
Package Power Dissipation = (TJ MAX – TA)/θJA
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the B and W terminals at a given resistance.Includes programming of nonvolatile memory.Applicable to TSSOP-16 only. For LFCSP-16, please consult factory for details.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADN2850 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDEADN2850BCP25
ADN2850BCP25-RL7
ADN2850BCP250
ADN2850BCP250-RL7
ADN2850BRU25
ADN2850BRU25-RL7
*Line 1 contains product number, ADN2850, line 2 Top Mark branding contains differentiating detail by part type, line 3 contains lot number, line 4 contains product
date code YYWW.
ADN2850
VSS
GNDV2
VDDRD
CLKSDIB1
SDO
ADN2850BCP PIN FUNCTION DESCRIPTIONS2GND
3VSS
4V1
5W1Wiper terminal of RDAC1 ADDR
ADN2850BRU PIN FUNCTION DESCRIPTIONS4GND
5VSS
6V1
7W1Wiper terminal of RDAC1. ADDR
PIN CONFIGURATIONS
Table I.24-Bit Serial Data-WordCommand bits are C0 to C3. Address bits are A3–A0. Data bits D0 to D9 are applicable to RDAC wiper register whereas D0 to D15 are applicable to EEMEM
Register. Command instruction codes are defined in Table II.
Table II.Instruction Operation Truth Table1, 2, 3NOTESThe SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or 10,
the selected internal register data will be present in data byte 0 and 1. The instructions following 9 and 10 must also be a full 24-bit data-word to completely clock out
the contents of the serial register.
ADN2850
OPERATIONAL OVERVIEWThe ADN2850 programmable resistor is designed to operate as
a true variable resistor. The resistor wiper position is determined
by the RDAC register contents. The RDAC register acts as a
scratch pad register which allows unlimited changes of resistance
settings. The scratch pad register can be programmed with any
position setting using the standard SPI serial interface by loading
the 24-bit data-word. The format of the data-word is that the firstbits are instructions, the following 4bits are addresses, and the
last 16bits are data. Once a specific value is set, this value can be
saved into a corresponding EEMEM register. During subsequent
power-ups, the wiper setting will automatically be loaded at that
value. Saving data to the EEMEM takes about 25 ms and con-
sumes approximately 20 mA. During this time the shift register
is locked, preventing any changes from taking place. The RDY pin
indicates the completion of this EEMEM saving process. There
are also 13 two-bytes addresses, of user defined data that can be
stored in EEMEM.
OPERATION DETAILThere are 16 instructions that facilitate users’ programming
needs. Referring to Table II, the instructions are:Do NothingRestore EEMEM setting to RDACSave RDAC setting to EEMEMSave user data or RDAC setting to EEMEMDecrement 6 dBDecrement all 6 dBDecrement one stepDecrement all one stepReset all EEMEM settings to RDACRead EEMEM to SDO
10.Read Wiper Setting to SDO
11.Write data to RDAC
12.Increment 6 dB
13.Increment all 6 dB
14.Increment one step
15.Increment all one step
Tables VIII to XIV provide a few programming examples by using
some of these instructions.
Scratch Pad and EEMEM ProgrammingThe basic mode of setting the programmable resistor wiper position
(programming the scratch pad register) is done by loading the
serial data input register with the instruction 11, the corresponding
address, and the data. Since the scratch pad register is a standard
logic register, there is no restriction on the number of changes
allowed. When the desired wiper position is determined, the user can
load the serial data input register with the instruction2, which stores
the setting into the corresponding EEMEM register. The EEMEM
value can be changed at any time or permanently protected by
activating the WP command. TableIII provides a programming
example listing the sequence of serial data input (SDI) words and
the corresponding serial data output (SDO) in hexadecimal format.
Table III.Set and Save RDAC with Independent Data
to EEMEM RegistersAt system power ON, the scratch pad register is automatically
refreshed with the value previously saved in the corresponding
EEMEM register. The factory preset EEMEM value is midscale.
During operations, the scratch pad register can also be refreshed
with the current contents of the EEMEM registers in three different
ways. First, executing instruction 1 retrieves the corresponding
EEMEM value. Second, executing instruction8 resets the EEMEM
values of both channels. Finally, pulsing the PR pin also refreshes
both EEMEM settings. Operating the hardware control PR
function, however, requires a complete pulse signal. When PR
goes low, the internal logic sets the wiper at midscale. The
EEMEM value will not be loaded until PR returns to high.
EEMEM ProtectionThe write-protect (WP) disables any changes of the scratch pad
register contents regardless of the software commands, except
that the EEMEM setting can be refreshed and can overwrite the
WP by using commands 1, 8, and PR pulse. To disable WP, it is
recommended to execute a NOP command before returning
WP to logic high.
Linear Increment and Decrement CommandsThe increment and decrement commands (14, 15, 6, 7) are useful
for linear step adjustment applications. These commands simplify
microcontroller software coding by allowing the controller to
just send an increment or decrement command to the device. The
adjustment can be individually or gang controlled. For incre-
ment command, executing instruction 14 will automatically move the
wiper to the next resistance segment position. The master increment
instruction 15 will move all resistor wipers up by one position.
Logarithmic Taper Mode Adjustment (�6 dB/step)There are four programming instructions which provide the
logarithmic taper increment and decrement wiper position con-
trol by either individual or gang control. 6 dB increment is
activated by instructions 12 and 13 and 6 dB decrement is acti-
vated by instructions 4 and 5. For example, starting at zero
scale, executing 11 times the increment instruction 12 will move
the wiper in 6dB per step from the 0% of the full-scaleRWB to
the full-scale RWB. The 6dB increment instruction doubles the
value of the RDAC register contents each time the command is
executed. When the wiper position is near the maximum setting,
the last 6dB increment instruction will cause the wiper to go to
the full-scale 1023-code position. Further 6 dB per increment
instruction will no longer change the wiper position beyond its
Using Additional Internal Nonvolatile EEMEMThe ADN2850 contains additional internal user storage registers
(EEMEM) for saving constants and other 16-bit data. TableV
provides an address map of the internal storage registers shown
in the functional block diagram as EEMEM1, EEMEM2, and
and 26 bytes (13 addresses � 2 bytes each) of USER EEMEM.
Table V. EEMEM Address MapNOTESRDAC data stored in EEMEM locations are transferred to their corresponding
RDAC REGISTER at power-on, or when instructions 1, 8, and PR are executed.Execution of instruction 1 leaves the device in the read mode power consumption
state. After the last instruction 1 is executed, the user should perform a NOP,
instruction 0 to return the device to the low power idling state.USER
are internal nonvolatile EEMEM registers available to store and
retrieve constants and other 16-bit information using instructions 3 and 9 respectively.Read only.
Calculating Actual Full-Scale Resistance
The actual tolerance of the rated full-scale resistance RWB1 is
stored in EEMEM register 15 during factory testing. The actual
full-scale resistance can therefore be calculated, which will be
valuable for tolerance matching or calibration. Notice this value
is read only, and the full-scale resistance of RWB2_FS matches
RWB1_FS, of typically 0.1%.
The tolerance in % is stored in the last 16 bits of data in EEMEM
register 15. The format is sign magnitude binary format with the
MSB designates for sign (0=positive and 1=negative), the nextMSB designate for the integer number, and the 8LSB designate
for the decimal number. See Table VI.
Table VI.Tolerance in % from Rated Full-Scale Resistance
For example, if RWB_FS_RATED = 250 kΩ and the data is 0001
1100 0000 1111, RWB_FS_ACTUAL can be calculated as follows:
MSB:0 = Positive
Next 7 MSB:001 1100 = 28
8 LSB:0000 1111 = 15 � 2–8 = 0.06
% Tolerance = +28.06%
Thus, RWB_FS_ACTUAL = 320.15 kΩ
conditions. Table IV illustrates the operation of the shifting
function on the individual RDAC register data bits. Each line
going down the table represents a successive shift operation. Note
that the left shift 12 and 13 commands were modified such that
if the data in the RDAC register is equal to zero, and the data is
left shifted, the RDAC register is then set to code 1. Similarly, if the
data in the RDAC register is greater than or equal to midscale,
and the data is left shifted, then the data in the RDAC register is
automatically set to fullscale. This makes the left shift function
as ideal a logarithmic adjustment as possible.
The right shift 4 and 5 commands will be ideal only if the LSB is
zero (i.e., ideal logarithmic—no error). If the LSB is a one, then
the right shift function generates a linear half LSB error, which
translates to a number of bits-dependent logarithmic error as
shown in Figure 3. The plot shows the error of the odd numbers
of bits for ADN2850.
Table IV.Detail Left and Right Shift Functions for 6dB
Step Increment and Decrement
Actual conformance to a logarithmic curve between the data con-
tents in the RDAC register and the wiper position for each right
shift 4 and 5 command execution contains an error only for odd
numbers of bits. Even numbers of bits are ideal. The graph in
Figure 3 shows plots of Log_Error [i.e., 20 � log10 (error/code)]
ADN2850. For example, code 3 Log_Error = 20 � log10 (0.5/3)
= –15.56 dB, which is the worst case. The plot of Log_Error is
more significant at the lower codes.
ADN2850
Daisy-Chain Operation
The serial data output pin (SDO) serves two purposes. It can be
used to read out the contents of the wiper settings or EEMEM
values using instructions 10 and 9 respectively. If these instruc-
tions are not used, SDO can be used for daisy-chaining multiple
devices in simultaneous operations (see Figure 4). The SDO pin
contains an open-drain N-Ch FET and requires a pull-up resis-
tor if SDO function is used. Users need to tie the SDO pin of
one package to the SDI pin of the next package. Users may need
to increase the clock period because the pull-up resistor and the
capacitive loading at the SDO-SDI interface may induce time
delay to the subsequent devices (see Figure 4). If two ADN2850s
are daisy-chained, a total 48 bits of data is required. The firstbits (formatted 4-bit instruction, 4-bit address, and 16-bit
data) go to U2 and the second 24bits with the same format go
to U1. The CS should be kept low until all 48 bits are clocked into
their respective serial registers. The CS is then pulled high to
complete the operation.
Figure 4.Daisy-Chain Configuration
DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD protected. Digital inputs are high
impedance and can be driven directly from most digital sources.
Active at logic low, PR and WP should be biased to VDD if they
are not used. There are no internal pull-up resistors present on
any digital input pins. To avoid floating digital pins that may
cause false triggering in a noisy environment, pull-up resistors
should be added to these pins. However, this only applies to the
case where the device will be detached from the driving source
once it is programmed.
The SDO and RDY pins are open-drain digital outputs. Similarly,
pull-up resistors are needed if these functions are used. To optimize
the speed and power trade-off, use 2.2 kΩ pull-up resistors.
The equivalent serial data input and output logic is shown in
Figure 5. The open-drain output SDO is disabled whenever
chip select CS is logic high. ESD protection of the digital inputs
is shown in Figures 6a and 6b.
Figure 5.Equivalent Digital Input-Output Logic
Figure 6a.Equivalent ESD Digital Input Protection
Figure 6b.Equivalent WP Input Protection
SERIAL DATA INTERFACE
The ADN2850 contains a 4-wire, SPI compatible, digital inter-
face (SDI, SDO, CS, and CLK). The 24-bit serial word must be
loaded with MSB first, and the format of the word is shown in
Table I. The Command Bits (C0 to C3) control the operation of
the programmable resistor according to the instruction shown
in Table II. A0 to A3 are assigned for address bits. A0 is used to
address RDAC1 or RDAC2. Addresses 2 to 14 are accessible by
users. Address 15 is reserved for the factory. TableV provides an
address map of the EEMEM locations. The data bits (D0 to D9) are
the values that are loaded into the RDAC registers at instruc-
tion11. The data bits (D0 to D15) are the values that are loaded
into the EEMEM registers at instruction3.
The last instruction prior to a period of no programming activity
should be applied with the No Operation (NOP), instruction 0. It
is recommended to do so to ensure minimum power consumption
in the internal logic circuitry
The SPI interface can be used in two slave modes, CPHA = 1,
