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ADM9690ARADN/a300avaiPower Supply and Watchdog Timer Monitoring Circuit


ADM9690AR ,Power Supply and Watchdog Timer Monitoring CircuitGENERAL DESCRIPTIONThe watchdog timer monitoring circuit is designed to monitorThe ADM9690 contains ..
ADM9690ARN ,Power Supply and Watchdog Timer Monitoring CircuitGENERAL DESCRIPTIONThe watchdog timer monitoring circuit is designed to monitorThe ADM9690 contains ..
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ADM9690AR
Power Supply and Watchdog Timer Monitoring Circuit
REV.A
Power Supply and Watchdog Timer
Monitoring Circuit
FUNCTIONAL BLOCK DIAGRAM
VCC
VMON
OSC SEL1
OSC SEL2
RESET(1)
RESET(2)
WATCHDOG
INPUT (WDI)
GND
FEATURES
Precision Voltage Monitor (4.31 V)
Watchdog Timeout Monitor
Selectable Watchdog Timeout—0.75 ms, 1.5 ms,
12.5 ms, 25 ms
Two RESET Outputs
APPLICATIONS
Microprocessor Systems
Computers
Printers
Controllers
Intelligent Instruments
GENERAL DESCRIPTION

The ADM9690 contains a voltage monitoring comparator and a
watchdog timer monitor. It is designed to monitor the 5V
power supply to a microprocessor and the microprocessor opera-
tion via a watchdog function.
The voltage monitoring comparator monitors the voltage on
VMON. If it drops outside tolerance, as will happen during a
power-fail, two reset signals are generated. Both reset signals go
active (low) simultaneously. They will remain active while
VMON is below the threshold, and for 50 ms (RESET(1)) or
60 ms (RESET(2)) after VMON climbs above the reset thresh-
old. RESET(1) is intended to provide a power-on reset signal
for the µP while RESET(2) is used to hold additional circuitry
in a reset state until the µP has regained control following a
power-up. The voltage monitoring circuitry remains operational
with VCC as low as 2 V.
The watchdog timer monitoring circuit is designed to monitor
the activity on the WDI input. This input is normally connected
to an output line on the µP. Its function is to check that the
microprocessor has not stalled in an infinite loop. If there is a
period of inactivity for the watchdog timeout period, both reset
outputs are activated. As above, RESET(1) remains low for
50 ms while RESET(2) remains low for an additional 10 ms.
The watchdog timer is restarted when RESET(1) goes inactive.
The actual watchdog timeout period is adjustable using two
select inputs SEL1 and SEL2.
The ADM9690 is available in an 8-lead SOIC package. It is
specified over the industrial temperature range.
ADM9690–SPECIFICATIONS
RESET AND WATCHDOG TIMER
WDI INPUT PULSEWIDTH
Specifications subject to change without notice.
(VCC = Full Operating Range. TA = TMIN to TMAX unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VMON . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Power Dissipation, R-8 SOIC . . . . . . . . . . . . . . . . . . 400 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Industrial (A Version) . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.
ORDERING GUIDE
PIN FUNCTION DESCRIPTIONS

VMON
GND
RESET(1)
RESET(2)
WDI
SEL1, 2PIN CONFIGURATION
ADM9690
–Typical Performance Curves

Figure 1.Reset Output Voltage vs. Supply
TEMPERATURE –
RESET VOLTAGE THRESHOLD
Volts
4.398

Figure 2.Reset Voltage Threshold vs. Temperature
Figure 5.Typical Application Circuit
VCC – Volts
WATCHDOG AND RESET TIMEOUT PERIOD
ms
6.06.5

Figure 3.Watchdog and Reset Timeout Period vs. Supply
@ –40°C
TEMPERATURE –
BATTERY SUPPLY CURRENT
69.2

Figure 4.Supply Current vs. Temperature
POWER SUPPLY AND WATCHDOG MONITORING
CIRCUIT

The ADM9690 contains a power supply voltage monitoring
comparator and a watchdog timer monitor. Either VMON drop-
ping outside tolerance or the watchdog timer timing out results
in a reset sequence as discussed below. Two reset outputs are
provided. RESET(1) and RESET(2).
POWER FAIL/POWER-ON RESET

When VMON falls below the reset threshold (4.4 V) both RESET
outputs are forced low immediately.
On power-up, RESET(1) will remain low for 50 milliseconds
after VMON rises above the reset threshold. This provides a
power-on reset for the microprocessor. RESET(2) remains
active low for an additional 10 ms. RESET(1) is intended to
VCC
VMON
OSC SEL1
OSC SEL2
RESET(1)
RESET(2)
WATCHDOG
INPUT (WDI)
GND

Figure 6.Functional Block Diagram
provide a power-on reset signal for the µP while RESET(2) is
used to hold additional circuitry in a reset state until the µP has
regained control following a power-up.
The guaranteed minimum and maximum thresholds for the
ADM9690 are 4.3 V and 4.5 V.
Watchdog Timer RESET

The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an infinite
loop. An output line on the processor may be used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, both RESET outputs are taken active
(low). RESET(1) remains low for 50 ms and RESET(2) re-
mains low for an additional 10 ms . Each transition (either
positive-going or negative-going) of WDI after RESET(1) has
gone inactive restarts the watchdog timer. The actual watchdog
timeout period is adjustable using SEL1 and SEL2. Four timeout
periods are selectable. Please refer to Table I.
The watchdog timer is restarted at the end of RESET(1)
(RESET(1) going high), whether the reset was caused by lack of
activity on WDI or by VMON falling below the reset threshold.
Table I.

Figure 7.Power-On RESET Timing
Figure 8.Watchdog RESET Timing
ADM9690
OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).
C3135a
3/00 (rev. A)
PRINTED IN U.S.A.
8-Lead Narrow Body SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
0.0196 (0.50)
0.0099 (0.25)x 45°
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