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ADM1066ACPANALOGN/a9avaiMulti- Supply Supervisor/Sequencer with Margining Control


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ADM1066ACP
Multi- Supply Supervisor/Sequencer with Margining Control
Super Sequencer™ with Margining Control
and Auxiliary ADC Inputs

Rev. 0
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
better than 1% accuracy
5 selectable input attenuators allow supervision:
Supplies up to 14.4 V on VH
Supplies up to 6 V on VP1–4
5 dual-function inputs, VX1–5:
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable output drivers (PDO1–10):
Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external
N-FET (PDO1–6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs:
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Complete voltage margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow
voltage adjustment via dc/dc converter trim/feedback
node
12-bit ADC for readback of all supervised voltages
2 auxiliary (single-ended) ADC inputs
Reference input, REFIN, has 2 input options:
Driven directly from 2.048V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VP1–4, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
40-lead 6 mm × 6 mm LFCSP and
48-lead 7 mm × 7 mm TQFP packages
FUNCTIONAL BLOCK DIAGRAM

PDO7
PDO8
PDO9
PDO10
PDOGND
VDDCAP
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
GND
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
AGND
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION

The ADM1066 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems. In addition to these
functions, the ADM1066 integrates a 12-bit ADC and six 8-bit
voltage output DACs. These circuits can be used to implement a
closed-loop margining system, which enables supply adjustment
by altering either the feedback node or reference of a dc/dc
converter using the DAC outputs.
(continued on Page 3)
TABLE OF CONTENTS
General Description.........................................................................3
Specifications.....................................................................................4
Pin Configurations and Function Descriptions...........................7
Absolute Maximum Ratings............................................................8
Thermal Characteristics..............................................................8
ESD Caution..................................................................................8
Typical Performance Characteristics.............................................9
Powering the ADM1066................................................................12
Inputs................................................................................................13
Supply Supervision.....................................................................13
Programming the Supply Fault Detectors...............................13
Input Comparator Hysteresis....................................................14
Input Glitch Filtering.................................................................14
Supply Supervision with VXn Inputs.......................................14
VXn Pins as Digital Inputs........................................................15
Outputs............................................................................................16
Supply Sequencing through Configurable Output Drivers..16
Sequencing Engine.........................................................................17
Overview......................................................................................17
Warnings......................................................................................17
SMBus Jump/Unconditional Jump..........................................17
Sequencing Engine Application Example...............................18
Sequence Detector......................................................................19
Monitoring Fault Detector........................................................19
Timeout Detector.......................................................................19
Fault Reporting...........................................................................19
Voltage Readback............................................................................20
Supply Supervision with the ADC...........................................20
Supply Margining...........................................................................21
Overview.....................................................................................21
Open-Loop Margining..............................................................21
Closed-Loop Supply Margining...............................................21
Writing to the DACs..................................................................22
Choosing the Size of the Attenuation Resistor.......................22
DAC Limiting/Other Safety Features......................................22
Applications Diagram....................................................................23
Communicating with the ADM1066...........................................24
Configuration Download at Power-Up...................................24
Updating the Configuration.....................................................24
Updating the Sequencing Engine.............................................25
Internal Registers........................................................................25
EEPROM.....................................................................................25
Serial Bus Interface.....................................................................25
Write Operations........................................................................27
Read Operations.........................................................................29
Outline Dimensions.......................................................................31
Ordering Guide..........................................................................31
REVISION HISTORY
10/04—Revision 0: Initial Version

GENERAL DESCRIPTION
(continued from Page 1)
Supply margining can be performed with a minimum of
external components. The margining loop can be used for in-
circuit testing of a board during production (for example, to
verify the board’s functionality at −5% of nominal supplies),
or can be used dynamically to accurately control the output
voltage of a dc/dc converter.
The device also provides up to ten programmable inputs for
monitoring under, over, or out-of-window faults on up to ten
supplies. In addition, ten programmable outputs can be used as
logic enables. Six of them can also provide up to a 12 V output
for driving the gate of an N-channel FET, which can be placed
in the path of a supply.
The logical core of the device is a sequencing engine. This state-
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by ADI.
SDASCLA1A0
REFOUTREFINAUX1AUX2REFGNDPDO1
PDO2
PDOGND
PDO3
DAC1
DAC6
VCCPGNDDAC2DAC3DAC4DAC5
PDO4
PDO5
PDO8
PDO9PDO6PDO7PDO10
VX2
VX3
VX4
VP2
VP3
VP4
VP1
VX1
SFDGND
VX5
VDDCAP
Figure 2. Detailed Block Diagram
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.

At least one of the VH, VP1-4 pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested, but is supported by characterization data at initial product release.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1066
TOP VIEW
(Not to Scale)
GND
DDCAP
AUX
AUX
CCP
PDOGND
AGND
FGND
FIN
FOUT
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PIN 1INDICATOR
Figure 3. LFCSP Pin Configuration
NC = NO CONNECT
GND
DCAP
AUX
AUX
PDOGND
AGND
FGND
FIN
FOUT
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
ABSOLUTE MAXIMUM RATINGS
Table 3.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS

40-lead LFCSP package: θJA = 25°C/W
48-lead TQFP package: θJA = 14.8°C/W
ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TYPICAL PERFORMANCE CHARACTERISTICS 54321
VVP1 (V)
VDDCAP
(V
Figure 5. VVDDCAP vs. VVP1
0161412108642

VVH (V)
DDCAP
(V
Figure 6. VVDDCAP vs. VVH
0.50123456

VVP1 (V)
IVP1
(mA)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
1000123456

VVP1 (V)
IVP1
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
0.50161412108642

VVH (V)
IVH
(mA)
Figure 9. IVH vs. VVH (VH as Supply)
1000654321

VVH (V)
IVH
Figure 10. IVH vs. VVH (VH Not as Supply)
015.012.510.07.55.02.5ILOAD CURRENT (µA)
PDO
CHARGE
Figure 11. VPDO1 (FET Drive Mode) vs. ILOAD
0.50654321

ILOAD (mA)
(V
Figure 12. VPDO1 (Strong Pull-Up VP) vs. ILOAD
0.50605040302010

ILOAD(µA)
PDO
(V
Figure 13. VPDO1 (Weak Pull-Up to VP) vs. ILOAD
40001000200030000

CODE
DNL (LS
Figure 14. DNL for ADC
CODE
INL (LSB)

Figure 15. INL for ADC
2000204920482047

CODE
HITS
CODE
Figure 16. ADC Noise, Midcode Input, 10,000 Reads
DACPROBEPOINT
20kΩ
Figure 17. Transient Response of DAC Code Change into Typical Load
DAC1V
PROBEPOINT
100kΩ
Figure 18. Transient Response of DAC to Turn-On from HI-Z State
0.995–40–20020406010080

TEMPERATURE (°C)
DAC OUTP
Figure 19. DAC Output vs. Temperature
–40–20020406010080

TEMPERATURE (°C)
FOUT (V
Figure 20. REFOUT vs. Temperature
POWERING THE ADM1066
The ADM1066 is powered from the highest voltage input on
either the positive-only supply inputs (VPn) or the high voltage
supply input (VH). This technique offers improved redundancy
as the device is not dependent on any particular voltage rail to
keep it operational. The same pins are used for supply fault
detection (discussed later in the next section). A VDD arbitrator
on the device chooses which supply to use. The arbitrator can
be considered an OR’ing of five LDOs together. A supply
comparator chooses which of the inputs is highest and selects
this one to provide the on-chip supply. There is minimal
switching loss with this architecture (~0.2 V), resulting in the
ability to power the ADM1066 from a supply as low as 3.0 V.
Note that the supply on the VXn pins cannot be used to power
the device.
An external capacitor to GND is required to decouple the on-
chip supply from noise. This capacitor should be connected to
the VDDCAP pin, as shown in Figure 21. The capacitor has
another use during brownouts (momentary loss of power).
Under these conditions, when the input supply (VPn or VH)
dips transiently below VDD, the synchronous rectifier switch
immediately turns off so that it does not pull VDD down. The
VDD cap can then act as a reservoir to keep the device active
until the next highest supply takes over the powering of the
device. 10 µF is recommended for this reservoir/decoupling
function.
Note that when two or more supplies are within 100 mV of each
other, the supply that takes control of VDD first keeps control.
For example, if VP1 is connected to a 3.3 V supply, then VDD
powers up to approximately 3.1 V through VP1. If VP2 is then
connected to another 3.3 V supply, VP1 still powers the device,
unless VP2 goes 100 mV higher than VP1.
VP4
VP3
VP2
VP1

Figure 21. VDD Arbitrator Operation
INPUTS
SUPPLY SUPERVISION

The ADM1066 has ten programmable inputs. Five of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VP1–4 by default. The other five inputs are
labeled VX1–VX5 and have dual functionality. They can be
used as either supply fault detectors, with similar functionality
to VH and VP1–4, or CMOS/TTL-compatible logic inputs to
the devices. Therefore, the ADM1066 can have up to ten analog
inputs, a minimum of five analog inputs and five digital inputs,
or a combination. If an input is used as an analog input, it
cannot be used as a digital input. Therefore, a configuration
requiring ten analog inputs has no digital inputs available.
Table 5 shows the details of each of the inputs.
023COMPARATOR
FAULT TYPESELECT
FAULTOUTPUT
VPn
MID
LOWSELECT
ULTRALOW

Figure 22. Supply Fault Detector Block
PROGRAMMING THE SUPPLY FAULT DETECTORS

The ADM1066 has up to ten supply fault detectors (SFDs) on its
ten input channels. These highly programmable reset generators
enable the supervision of up to ten supply voltages. The supplies
can be as low as 0.573 V and as high as 14.4 V. The inputs can be
configured to detect an undervoltage fault (the input voltage
droops below a preprogrammed value), an overvoltage fault (the
input voltage rises above a preprogrammed value) or an out-of-
window fault (undervoltage or overvoltage). The thresholds can
be programmed to an 8-bit resolution in registers provided in
the ADM1066. This translates to a voltage resolution that is
dependent on the range selected.
The resolution is given by
Step Size = Threshold Range/255
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
(14.4 V − 4.8 V)/255 = 37.6 mV
Table 4 lists the upper and lower limit of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 4. Voltage Range Limits

The threshold value required is given by
VT = (VR × N)/255 + VB
where:
VT is the desired threshold voltage (UV or OV).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is given
by
N = 255 × (VT − VB)/VR
For example, if the user wants to set a 5 V OV threshold on VP1,
the code to be programmed in the PS1OVTH register
(discussed in the AN-698 application note) is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
Table 5. Input Functions, Thresholds, and Ranges
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 22 are always
looking at VPn. To avoid chattering (multiple transitions when
the input is very close to the set threshold level), these compara-
tors have digitally programmable hysteresis. The hysteresis can
be programmed up to the values shown in Table 5.
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program how much above
the UV threshold the input must rise again before a UV fault is
deasserted. Similarly, the user can program how much below the
OV threshold an input must fall again before an OV fault is
deasserted.
The hysteresis figure is given by
VHYST = VR × NTHRESH/255
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 5.
INPUT GLITCH FILTERING

The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators.
This allows the user to remove any spurious transitions such as
supply bounce at turn-on. The glitch filter function is additional
to the digitally programmable hysteresis of the SFD compara-
tors. The glitch filter timeout is programmable up to 100 µs.
For example, when the glitch filter timeout is 100 µs, any pulses
appearing on the input of the glitch filter block that are less than
100 µs in duration are prevented from appearing on the output
of the glitch filter block. Any input pulse that is longer than
100 µs does appear on the output of the glitch filter block. The
output is delayed with respect to the input by 100 µs. The
filtering process is shown in Figure 23.
04609-024T0T0TGF
INPUT PULSE SHORTERTHAN GLITCH FILTER TIMEOUTINPUT PULSE LONGERTHAN GLITCH FILTER TIMEOUT
PROGRAMMEDTIMEOUTPROGRAMMEDTIMEOUT

Figure 23. Input Glitch Filter Function
SUPPLY SUPERVISION WITH VXn INPUTS

The VXn inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as an
analog (SFD) input, the VXn pins have very similar functionality
to the VH and VPn pins. The major difference is that the VXn
pins have only one input range: 0.573 V to 1.375 V. Therefore,
these inputs can directly supervise only the very low supplies.
However, the input impedance of the VXn pins is high, allowing
an external resistor divide network to be connected to the pin.
Thus, any supply can be potentially divided down into the input
range of the VXn pin and supervised. This enables the ADM1066
to monitor other supplies such as +24 V, +48 V, and −5 V.
An additional supply supervision function is available when the
VXn pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedi-
cated analog inputs, VP1–4 and VH. The analog function of
VX1 is mapped to VP1, VX2 is mapped to VP2, and so on. VX5
is mapped to VH. In this case, these SFDs can be viewed as a
secondary or warning SFD.
The secondary SFDs are fixed to the same input range as the
primary SFD. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be gener-
ated on a single supply using only one pin. For example, if VP1
is set to output a fault if a 3.3 V supply droops to 3.0 V, VX1 can
be set to output a warning at 3.1 V. Warning outputs are available
for readback from the status registers. They are also OR’ed
together and fed into the sequencing engine (SE), allowing
warnings to generate interrupts on the PDOs. Therefore, in the
example above, if the supply droops to 3.1 V, a warning is
generated, and remedial action can be taken before the supply
drops out of tolerance.
VXn PINS AS DIGITAL INPUTS
As mentioned previously, the VXn input pins on the ADM1066
have dual functionality. The second function is as a digital input
to the device. Therefore, the ADM1066 can be configured for up
to five digital inputs. These inputs are TTL/CMOS-compatible.
Standard logic signals can be applied to the pins: RESET from
reset generators, PWRGOOD signals, fault flags, manual resets,
and so on. These signals are available as inputs to the SE, and so
can be used to control the status of the PDOs. The inputs can be
configured to detect either a change in level or an edge.
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, once the logic transition is detected, a pulse of
programmable width is output from the digital block. The width
is programmable from 0 µs to 100 µs.
The digital blocks feature the same glitch filter function that is
available on the SFDs. This enables the user to ignore spurious
transitions on the inputs. For example, the filter can be used to
debounce a manual reset switch.
When configured as digital inputs, each of the VXn pins has a
weak (10 µA) pull-down current source available for placing the
input in a known condition, even if left floating. The current
source, if selected, weakly pulls the input to GND.
VXn(DIGITAL INPUT)SEQUENCINGENGINE
Figure 24. VXn Digital Input Function
OUTPUTS
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS

Supply sequencing is achieved with the ADM1066 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing
engine (SE). The SE determines what action is to be taken with
the PDOs based on the condition of the inputs of the ADM1066.
Therefore, the PDOs can be set up to assert when the SFDs are
in tolerance, the correct input signals are received on the VXn
digital pins, no warnings are received from any of the inputs of
the device, and so on. The PDOs can be used for a variety of
functions. The primary function is to provide enable signals for
LDOs or dc/dc converters, which generate supplies locally on a
board. The PDOs can also be used to provide a POWER_GOOD
signal when all the SFDs are in tolerance, or a RESET output if
one of the SFDs goes out of specification (this can be used as a
status signal for a DSP, FPGA, or other microcontroller).
The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as follows: Open-drain (allowing the user to connect an external pull-up
resistor) Open-drain with weak pull-up to VDD Push/pull to VDD Open-drain with weak pull-up to VPn Push/pull to VPn Strong pull-down to GND Internally charge-pumped high drive (12 V, PDO1–6 only)
The last option (available only on PDO1–6) allows the user to
directly drive a voltage high enough to fully enhance an external
N-FET, which is used to isolate, for example, a card-side voltage
from a backplane supply (a PDO can sustain greater than 10.5 V
into a 1 µA load). The pull-down switches can also be used to
drive status LEDs directly.
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PnPDOCFG con-
figuration register (see the AN-698 application note for details).
The data sources are Output from the SE. Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence. On-Chip Clock. A 100 kHz clock is generated on the device.
This clock can be made available on any of the PDOs. It can
be used, for example, to clock an external device such as
an LED.
By default, the PDOs are pulled to GND by a weak (20 kΩ) on-
chip pull-down resistor. This is also the condition of the PDOs
on power-up, until the configuration is downloaded from
EEPROM and the programmed setup is latched. The outputs
are actively pulled low once a supply of 1 V or greater is on VPn
or VH. The outputs remain high impedance prior to 1 V appear-
ing on VPn or VH. This provides a known condition for the
PDOs during power-up. The internal pull-down can be over-
driven with an external pull-up of suitable value tied from the
PDO pin to the required pull-up voltage. The 20 kΩ resistor
must be accounted for in calculating a suitable value. For
example, if PDOn must be pulled up to 3.3 V, and 5 V is available
as an external supply, the pull-up resistor value is given by
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 = 10 kΩ
PDO
SE DATA
CFG4CFG5CFG6
CLK DATA
VP1SEL
VP4
VDD
Figure 25. Programmable Driver Output
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