ADM1026JST ,Complete Thermal and System Management ControllerSPECIFICATIONSParameter Min Typ Max Units Test Conditions/CommentsPOWER SUPPLYSupply Voltage, 3.3V ..
ADM1026JST-REEL ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsCharacteristics ........ 5 Analog Output.... 22 ESD Caution. 5 Fan Speed Measurement ..... 25 Pin C ..
ADM1026JST-REEL7 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsCharacteristics 8 NAND Tree Tests 31 Product Description........ 10 Using the ADM1026 ... 33 Funct ..
ADM1026JSTZ ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsFEATURES Full SMBus 1.1 support includes packet error checking (PEC) Chassis intrusion detection Up ..
ADM1026JSTZ-REEL ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsSpecifications.... 3 Measurement Inputs ... 16 Absolute Maximum Ratings...... 5 Temperature Measure ..
ADM1026JSTZ-REEL7 ,Highly Integrated Thermal and System Monitor for Servers/High Reliability SystemsSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
AH11 , High Dynamic Range Dual Amplifier
AH1-1 , High Dynamic Range Amplifier
AH110-89 , 0.2 Watt, High Linearity InGaP HBT Amplifier
AH114-89G , ¼ Watt, High Linearity InGaP HBT Amplifier
AH115-S8 , 1/2 Watt, High Linearity InGaP HBT Amplifier
AH116-S8 , 1/2 Watt, High Linearity InGaP HBT Amplifier
ADM1026JST
Complete Thermal and System Management Controller
Complete Thermal and SystemManagement Controller
FEATURES
Up to 19 Analog Measurement Channels (Including Inter-
nal Measurements)
Up to 8 Fan Speed Measurement Channels
Up to 17 General-Purpose Logic I/O Pins
Remote Temperature Measurement with Remote Diode
(Two Channels)
On-Chip Temperature Sensor
Analog and PWM Fan Speed Control Outputs
2-wire serial System Management Bus (SMBus)
8K bytes on-chip E2PROM
Full SMBus 1.1 support including Packet Error Checking
(PEC)
FUNCTIONAL BLOCK DIAGRAMREV. PrP 9/01
Chassis Intrusion Detection
Interrupt Output (SMBAlert)
Reset Input, Reset Outputs
Thermal Interrupt (THERM) Output
Shutdown Mode to Minimize Power Consumption
Limit Comparison of all Monitored Values
APPLICATIONS
Network Servers and Personal Computers
Telecommunications Equipment
Test Equipment and Measuring Instruments
PRELIMINARY TECHNICAL DATA
TEMP. -TO-DIGITAL CONVERTER
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
ADM1026–SPECIFICATIONS(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted)
PRODUCT DESCRIPTIONThe ADM1026 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various
system parameters. The ADM1026 has up to 19 analog measurement channels. Fifteen analog voltage inputs are provided, of which five are dedi-
cated to monitoring +3.3V, +5V and ±12V power supplies and the processor core voltage. The ADM1026 can monitor two further power-supply
voltages by measuring its own analog and digital VCC. One input (two pins) is dedicated to a remote temperature-sensing diode. Two further pins
can be configured as general-purpose analog inputs to measure 0 to 2.5V, or as a second temperature sensing input.The 8 remaining inputs are
general-purpose analog inputs with a range of 0 to 2.5V or 0 to 3V. Finally, the ADM1026 has on on-chip temperature sensor.
The ADM1026 has eight pins that can be configured for fan-speed measurement or as general purpose logic I/O pins. A further 8 pins are dedi-
cated to general-purpose logic I/O. An additional pin can be configured as a general purpose I/O or as the bidirectional ����� pin.
Measured values can be read out via a 2-wire serial System Management Bus, and values for limit comparisons can be programmed in over the
same serial bus. The high-speed successive-approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response
to any out-of-limit measurement.
The ADM1026’s 3V to 5.5V supply voltage range, low supply current, and serial interface make it ideal for a wide range of applications. These
include hardware monitoring and protection applications in personal computers, telecommunications equipment, and office electronics.
PRELIMINARY TECHNICAL DATA
PRELIMINARY TECHNICAL DATA
Specifications (Continued)
OPEN-DRAIN SERIAL DATA
BUS OUTPUT (SDA)���������,
EEPROM RELIABILITYEndurance
ADM1026
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS*Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . .6.5 V
Voltage on 12V VIN Pin . . . . . . . . . . . . . . . . . . . . . . . .+20V
Voltage on -12V VIN Pin . . . . . . . . . . . . . . . . . . . . . . .-20V
Voltage on Analog Pins . . . . . . . . . .-0.3V to (VCC+0.3V)
Voltage on Open Drain Digital Pins . . . . . .-0.3V to 6.5V
Input Current at any pin . . . . . . . . . . . . . . . . . . . . . .±5mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . .±20mA
Maximum Junction Temperature (TJmax) . . . . . . .150 °C
Storage Temperature Range . . . . . . . . .–65°C to +150°C
Lead Temperature, Soldering
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infra-Red 15 sec . . . . . . . . . . . . . . . . . . . . . . . . .+200°C
ESD Rating -12VIN pin . . . . . . . . . . . . . . . . . . . . .1000 V
ESD Rating all other pins . . . . . . . . . . . . . . . . . . .2000 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
THERMAL CHARACTERISTICS48-Pin LQFP Package:
θJA = 50°C/Watt, θJC = 10°C/Watt
ORDERING GUIDE
TemperaturePackagePackage
ModelRangeDescriptionOptionADM1026JST0°C to +100°C48-Pin LQFPST48tF
SCL
SDA
PIN CONFIGURATION
GPIO9
GPIO8
FAN0/GPIO0
FAN1/GPIO1
FAN2/GPIO2
FAN3/GPIO3
3.3V MAIN
DGND
FAN4/GPIO4
FAN5/GPIO5
FAN6/GPIO6
FAN7/GPIO7���
���
AIN5(0 - 3V)
AIN6(0 - 2.5V)
AIN7(0 - 2.5V)
VCCP(0 - 3V)
+12VIN(0 - 16V)
-12VIN(0 - 16V)
+5VIN(0 - 6.66V)
+VBAT(0 - 4.4V)
D2+/AIN8(0 - 2.5V)
D2-/AIN9(0 - 2.5V)
D1+
D1-/NTESTIN
/��
- 3
- 3
- 3
- 3
- 3
NOTESAll voltages are measured with respect to GND, unless otherwise specifiedTypicals are at TA=25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3VTUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators. VBAT input is only linear for VBAT
voltages greater than 1.5V.Total analog monitoring cycle time is nominally 273ms, made up of 18 � 11.38ms measurements on analog input and internal temperature channels, and 2 � 34.13ms
measurements on external temperature channels.The total fan count is based on 2 pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and the
fan speed. See section on Fan Speed Monitoring for more details.ADD is a three-state input that may be pulled high, low or left open-circuit.Logic inputs will accept input high voltages up to 5V even when device is operating at supply voltages below 5V.Timing specifications are tested at logic levels of VIL = 0.8V for a falling edge and VIH = 2.1V for a rising edge.Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, 25°C and 85°C. Typical Endurance at 25°C is 700,000 cycles.Retention lifetime equivalent at junction temperature (Tj) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6eV will
derate with junction temperature as shown in Figure 2.
Specifications (Continued)
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTION
ADM1026
PRELIMINARY TECHNICAL DATA
NOTESGPIO pins are open-drain and require external pullup resistors.
PRELIMINARY TECHNICAL DATA
FUNCTIONAL DESCRIPTION
GENERAL DESCRIPTIONThe ADM1026 is a complete system hardware monitor for
microprocessor-based systems. The device communicates
with the system via a serial System Management Bus. The
serial bus controller has a hardwired address line for device
selection (ADD, pin 15), a serial data line for reading and
writing addresses and data (SDA, pin 14), and an input line
for the serial clock (SCL, pin 13). All control and pro-
gramming functions of the ADM1026 are performed over
the serial bus.
MEASUREMENT INPUTSProgrammability of the analog and digital measurement
inputs makes the ADM1026 extremely flexible and versa-
tile. The device has an 8 bit A-to-D converter, and 17
analog measurement input pins that can be configured in
different ways.
Pins 25 and 26 are dedicated temperature inputs and may
be connected to the cathode and anode of a remote tem-
perature-sensing diode.
Pins 27 and 28 may be configured as a temperature input
and connected to a second temperature-sensing diode, or
they may be re-configured as analog inputs with a range of
0 to +2.5V.
Pins 29 to 33 are dedicated analog inputs with on-chip at-
tenuators, configured to monitor VBAT, +5V, -12V, +12V,
and the processor core voltage VCCP, respectively.
Pins 34 to 41 are general-purpose analog inputs with a
range of 0 to +2.5V or 0 to +3V. These are mainly in-
tended for monitoring SCSI termination voltages, but may
be used for other purposes.
The ADC also accepts input from an on-chip bandgap tem-
perature sensor that monitors system ambient temperature.
Finally, the ADM1026 monitors the supply from which it
is powered, 3.3VSTBY, so there is no need for a separate
pin to monitor this power supply voltage.
The ADM1026 has 8 pins that are general-purpose logic
I/O pins (pins 1,2 and 43 to 48), a pin that can be config-
ured as GPIO or as a bidirectional thermal interrupt
(�����) pin (pin 42) and 8 pins that can be configured
for fan speed measurement or as general-purpose logic
pins (pins 3 to 6 and 9 to 12).
SEQUENTIAL MEASUREMENTWhen the ADM1026 monitoring sequence is started, it
cycles sequentially through the measurement of analog in-
puts and the temperature sensor, while at the same time
the fan speed inputs are independently monitored. Mea-
sured values from these inputs are stored in Value Regis-
ters. These can be read out over the serial bus, or can be
compared with programmed limits stored in the Limit
Registers. The results of out of limit comparisons are
stored in the Interrupt Status Registers, and will generate
CHASSIS INTRUSIONA chassis intrusion input (pin 16) is provided to detect
unauthorised tampering with the equipment. This event is
latched in a battery-backed register bit.
RESETSThe ADM1026 has two power on reset outputs,
����������and ���������, that are asserted when
3.3VMAIN or 3.3VSTBY fall below the reset threshold.
These give a 180ms reset pulse at power up. ���������
also functions as an active-low ����� input.
FAN SPEED CONTROL OUTPUTSThe ADM1026 has two outputs intended to control fan
speed, though they can also be used for other purposes.
Pin 18 is an open-drain pulse-width modulated (PWM)
output with a programmable duty-cycle and an output
frequency of 75Hz.
Pin 23 is connected to the output of an on-chip, 8-bit
digital-to-analog converter with an output range of zero to
2.5V.
Either or both of these outputs may be used to implement
a temperature-controlled fan by controlling the speed of a
fan dependent upon the temperature measured by the on-
chip temperature sensor or remote temperature sensors.
INTERNAL REGISTERS OF THE ADM1026The ADM1026 contains a large number of data registers.
A brief description of the principal registers is given be-
low. More detailed descriptions are given in the relevant
sections and in the tables at the end of the data sheet.
Address Pointer Register: This register contains the address
that selects one of the other internal registers. When writing to
the ADM1026, the first byte of data is always a register ad-
dress, which is written to the Address Pointer Register.
Configuration Registers: Provide control and configuration
for various operating parameters of the ADM1026.
Fan Divisor Registers: Contain counter pre-scaler valuesfor fan speed measurement.
DAC/PWM Control Registers: Contain speed values forPWM and DAC fan drive outputs.
GPIO Configuration Registers: These configure theGPIO pins as input or output and for signal polarity.
Value and Limit Registers: The results of analog voltageinputs, temperature and fan speed measurements are
stored in these registers, along with their limit values.
Status Registers: These registers store events from the
various interrupt sources.
Mask Registers: Allow masking of individual interruptsources.
EEPROMThe ADM1026 has 8K bytes of non-volatile, Electrically-
ADM1026
PRELIMINARY TECHNICAL DATAthe volatile registers. Although referred to as Read Only
Memory, the EEPROM can be written to (as well as read
from) via the serial bus in exactly the same way as the
other registers. The only major differences between the2PROM and other registers are:An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.Writing to EEPROM is slower than writing to RAM.Writing to the EEPROM should be restricted because
it has a limited write/cycle life of 100,000 write opera-
tions, due to the usual EEPROM wear-out
mechanisms.
The E2PROM in the ADM1026 has been qualified for
two key E2PROM memory characteristics:- memory
cycling endurance and memory data retention.
Endurance qualifies the ability of the E2PROM to be
cycled through many Program, Read and Erase cycles. In
real terms, a single endurance cycle is composed of four
independent, sequential events. These events are defined
as follows:
(a)initial page erase sequence
(b) read/verify sequence
(c) program sequence
(d) second read/verify sequence
In reliability qualification, every byte is cycled from 00h
to FFh until a first fail is recorded signifying the
endurance limit of the E2PROM memory.
Retention quantifies the ability of the memory to retain its
programmed data over time. The E2PROM in the
ADM1026 has been qualified in accordance with the
formal JEDEC Retention Lifetime Specification (A117) at
a specific junction temperature (Tj = 55°C). As part of
this qualification procedure, the E2PROM memory is
cycled to its specified endurance limit described above,
before data retention is characterized. This means that the2PROM memory is guaranteed to retain its data for its
full specified retention lifetime every time the E2PROM is
reprogrammed. It should be noted that retention lifetime
based on an activation energy of 0.6eV will derate with Tj
as shown in Figure 2.
Figure 2. E2PROM Memory Retention
SERIAL BUS INTERFACEControl of the ADM1026 is carried out via the serial Sys-
tem Management Bus (SMBus). The ADM1026 is con-
nected to this bus as a slave device, under the control of a
master device.
The ADM1026 has a 7-bit serial bus slave address. When
the device is powered up, it will do so with a default serial
bus address. The five MSB's of the address are set to
01011, the two LSB's are determined by the logical states
of pin 15 (ADD/NTESTOUT). This is a three-state in-
put that can be grounded, connected to VCC or left open-
circuit to give three different addresses.
TABLE 1. ADDRESS PIN TRUTH TABLEADD PinA1A0
GND00
No Connect10
VCC01
SCL
SDA
ACK. BY
SLAVE
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND CODE91
ACK. BY
SLAVE
ACK. BY
STOP BY99
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK. BY
PRELIMINARY TECHNICAL DATAIf ADD is left open-circuit the default address will be
0101110. ADD is sampled only at power-up, so any changes
made while power is on will have no immediate effect.
The facility to make hardwired changes to device address
allows the user to avoid conflicts with other devices shar-
ing the same serial bus, for example if more than one
ADM1026 is used in a system.
GENERAL SMBUS TIMINGFigures 3a and 3b show timing diagrams for general read
and write operations using the SMBus. The SMBus speci-
fication defines specific conditions for different types of
read and write operation, which are discussed later.
The general SMBus protocol operates as follows:The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. This indicates that a data stream
will follow. All slave peripherals connected to the serial
bus respond to the START condition, and shift in the
next 8 bits, consisting of a 7-bit slave address (MSB
first) plus a R/� bit, which determines the direction of
the data transfer, i.e. whether data will be written to or
read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit, and holding it low dur-
ing the high period of this clock pulse. All other de-
vices on the bus now remain idle whilst the selected
device waits for data to be read from or written to it. If
the R/� bit is a 0 then the master will write to the slave
device. If the R/� bit is a 1 the master will read from
the slave device.Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal
after the slave address is a command byte. This tells the
slave device what to expect next. It may be an instruc-
tion such as telling the slave device to expect a block
write, or it may simply be a register address that tells
the slave where subsequent data is to be written.
Since data can flow in only one direction as defined by
the R/� bit, it is not possible to send a command to a
slave device during a read operation. Before doing a
read operation, it may first be necessary to do a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.When all data bytes have been read or written, stop con-
ditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the mas-
ter device will release the SDA line during the low pe-
riod before the 9th clock pulse, but the slave device will
not pull it low. This is known as No Acknowledge. The
master will then take the data line low during the low
period before the 10th clock pulse, then high during the
10th clock pulse to assert a STOP condition.
Note:
If it is required to perform several read or write operations
in succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
SMBUS PROTOCOLS FOR RAM AND EEPROMThe ADM1026 contains volatile registers (RAM) and
non-volatile EEPROM. RAM occupies address locations
from 00h to 6Fh, whilst EEPROM occupies addresses
from 8000h to 9FFFh.
Data can be written to and read from both RAM and
EEPROM as single data bytes and as block (sequential)
read or write operations of 32 data bytes, which is the
maximum block size allowed by the SMBus specification.
Data can only be written to unprogrammed EEPROM lo-
cations. To write new data to a programmed location it is
SCL
SDA
ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
DATA BYTE91
ACK. BY
SLAVE
NO ACK. STOP BY
MASTER
FRAME N
DATA BYTE99
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK. BY
MASTER
FRAME 3
DATA BYTEFigure 3b. General SMBus Read Timing Diagram
ADM1026
PRELIMINARY TECHNICAL DATAEEPROM Registers 1, 2 and 3 at addresses 06h, 0Ch and
13h. EEPROM Registers 1 and 2 are for factory use only.
EEPROM Register 3 is used to set up the EEPROM op-
erating mode.
Setting bit 0 of EEPROM Register 3 puts the EEPROM
into Read Mode. Setting bit 1 puts it into Programming
Mode. Setting Bit 2 puts it into Erase Mode.
One, and only one of these bits must be set before the
EEPROM may be accessed, setting no bits or more than
one of them will cause the device to respond with No Ac-
knowledge if an EEPROM read, program or erase opera-
tion is attempted.
It is important to distinguish between SMBus write opera-
tions such as sending an address or command, and
EEPROM programming operations. It is possible to write
an EEPROM address over the SMBus whatever the state
of EEPROM register 3. However, EEPROM Register 3
must be correctly set before a subsequent EEPROM op-
eration can be performed. For example, when reading
from the EEPROM, bit 0 of EEPROM Register 3 can be
set, even though SMBus write operations are required to
set up the EEPROM address for reading.
Bit 3 of EEPROM Register 3 is used for EEPROM write
protection. Setting this bit will prevent accidental pro-
gramming or erasure of the EEPROM. If a an EEPROM
write or erase operation is attempted with this bit set, the
ADM1026 will respond with No Acknowledge. This bit is
write once and can only be cleared by power-on reset.
EEPROM Register bit 7 is used for clock extend. Pro-
gramming an EEPROM byte takes approximately 250µs,
which would limit the SMBus clock for repeated or block
write operations. Since EEPROM block read/write access
is slow, it is recommended that this Clock Extend bit
normally be set to 1. This allows the ADM1026 to pull
SCL low and extend the clock pulse when it cannot accept
any more data.
*Although the EEPROM is arranged into 128 pages, only
124 pages are available to the user. The last 4 pages are
reserved for manufacturing purposes and cannot be erased/
rewritten.
ADM1026 WRITE OPERATIONSThe SMBus specification defines several protocols for dif-
ferent types of read and write operations. The ones used in
the ADM1026 are discussed below. The following abbre-
viations are used in the diagrams:-START-STOP-READ-WRITE-ACKNOWLEDGE-NO ACKNOWLEDGE
The ADM1026 uses the following SMBus write protocols:The master device asserts a start condition on SDA.The master sends the 7-bit slave address followed by
the write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code.The slave asserts ACK on SDA.The master asserts a STOP condition on SDA and the
transaction ends.
In the ADM1026, the send byte protocol is used to write a
register address to RAM for a subsequent single byte read
from the same address or block read or write starting at
that address. This is illustrated in Figure 4a.
3456Figure 4a. Setting A RAM Address For Subsequent Read
If it is required to read data from the RAM immediately
after setting up the address, the master can assert a repeat
start condition immediately after the final ACK and carry
out a single byte read, block read or block write opera-
tion, without asserting an intermediate stop condition.
Write Byte/WordIn this operation the master device sends a command byte
and one or two data bytes to the slave device, as follows:The master device asserts a start condition on SDA.The master sends the 7-bit slave address followed by
the write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code.The slave asserts ACK on SDA.The master sends a data byte.The slave asserts ACK on SDA.The master sends a data byte (or may assert STOP at
this point).The slave asserts ACK on SDA.
10.The master asserts a STOP condition on SDA to end
the transaction.
In the ADM1026, the write byte/word protocol is used for
four purposes. The ADM1026 knows how to respond by
the value of the command byte and EEPROM register 3.Write a single byte of data to RAM. In this case the
command byte is the RAM address from 00h to 6Fh
and the (only) data byte is the actual data. This is il-
lustrated in Figure 4b.
2345678
PRELIMINARY TECHNICAL DATA
the high byte of the EEPROM address from 80h to
9Fh. The (only) data byte is the low byte of the
EEPROM address. This is illustrated in Figure 4c.345678
Figure 4c. Setting An EEPROM Address
If it is required to read data from the EEPROM imme-
diately after setting up the address, the master can as-
sert a repeat start condition immediately after the final
ACK and carry out a single byte read, block read or
block write operation, without asserting an intermedi-
ate stop condition. In this case bit 0 of EEPROM Reg-
ister 3 should be set.Erase a page of EEPROM memory. EEPROM
memory can be written to only if it is unprogrammed.
Before writing to one or more EEPROM memory lo-
cations that are already programmed, the page or pages
containing those locations must first be erased.
EEPROM memory is erased by writing an EEPROM
page address plus an arbitrary byte of data with bit 2 of
EEPROM Register 3 set to 1.
As the EEPROM consists of 128 pages of 64 bytes, the
EEPROM page address consists of the EEPROM ad-
dress high byte (from 80h to 9Fh) and the two MSB's
of the low byte. The lower 6 bits of the EEPROM ad-
dress low byte only specify addresses within a page and
are ignored during an erase operation.345678910
Figure 4d. EEPROM Page Erasure
Page erasure takes approximately 20ms. If the
EEPROM is accessed before erasure is complete, it
will respond with No Acknowledge.Write a single byte of data to EEPROM. In this case
the command byte is the high byte of the EEPROM
address from 80h to 9Fh. The first data byte is the low
byte of the EEPROM address and the second data byte
is the actual data. Bit 1 of EEPROM Register 3 must
be set. This is illustrated in Figure 4e.345678910
Figure 4e. Single Byte Write To EEPROM
Block Write
In this operation the master device writes a block of data
to a slave device. The start address for a block write must
previously have been set. In the case of the ADM1026 thisThe master sends the 7-bit slave address followed by
the write bit (low).The addressed slave device asserts ACK on SDA.The master sends a command code that tells the slave
device to expect a block write. The ADM1026 com-
mand code for a block write is A0h (10100000).The slave asserts ACK on SDA.The master sends a data byte (20h) that tells the slave
device 32 data bytes will be sent to it. The master
should always send 32 data bytes to the ADM1026.The slave asserts ACK on SDA.The master sends 32 data bytes.
9.The slave asserts ACK on SDA after each data byte.
10. The master sends a PEC (Packet Error Checking)
byte.
11. The ADM1026 checks the PEC byte and issues an
ACK if correct. If incorrect (NACK), the master should
resend the data bytes.
12. The master asserts a STOP condition on SDA to end
the transaction.
Figure 4f. Block Write To EEPROM Or RAM
When performing a block write to EEPROM, bit 1 of
EEPROM Register 3 must be set.
Unlike some EEPROM devices which limit block writes to
within a page boundary, there is no limitation on the start ad-
dress when performing a block write to EEPROM, except:
1. There must be at least 32 locations from the start ad-
dress to the highest EEPROM address (9FFF), to avoid-
ing writing to invalid addresses.
2. If the addresses cross a page boundary, both pages must
be erased before programming.
ADM1026 READ OPERATIONS
The ADM1026 uses the following SMBus read protocols:
RECEIVE BYTE
In this operation the master device receives a single byte
from a slave device, as follows:
1.The master device asserts a START condition on SDA.
2.The master sends the 7-bit slave address followed by the
read bit (high).
3.The addressed slave device asserts ACK on SDA.
4.The master receives a data byte.
5.The master asserts NO ACK on SDA.
6.The master asserts a STOP condition on SDA and the
transaction ends.
ADM1026
PRELIMINARY TECHNICAL DATA
write byte/word operation. This is illustrated in Figure 4g.
When reading from EEPROM, Bit 0 of EEPROM
register 3 must be set.3456
Figure 4g. Single Byte Read From EEPROM Or RAM
BLOCK READ
In this operation the master device reads a block of data
from a slave device. The start address for a block read
must previously have been set. In the case of the
ADM1026 this is done by a Send Byte operation to set a
RAM address, or a Write Byte/Word operation to set an
EEPROM address. The block read operation itself
consists of a Send Byte operation that sends a block read
command to the slave, immediately followed by a repeated
start and a read operation that reads out multiple data
bytes, as follows:
1.The master device asserts a START condition on SDA.
2.The master sends the 7-bit slave address followed by the
write bit (low).
3.The addressed slave device asserts ACK on SDA.
4.The master sends a command code that tells the slave
device to expect a block read. The ADM1026 command
code for a block read is A1h (10100001).
5.The slave asserts ACK on SDA.
6.The master asserts a repeat start condition on SDA.
7.The master sends the 7-bit slave address followed by the
read bit (high).
8.The slave asserts ACK on SDA.
9.The ADM1026 sends a byte count data byte that tells
the master how many data bytes to expect. The ADM1026
will always return 32 data bytes (20h), which is the
maximum allowed by the SMBus 1.1 specification.
10.The master asserts ACK on SDA.
11.The master receives 32 data bytes.
12.The master asserts ACK on SDA after each data byte.
13.The ADM1026 issues a PEC byte to the master. The
master should check the PEC byte and issue another block
read if the PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the
end of the read.
15.The master asserts a STOP condition on SDA to end
the transaction.
Note: Although the ADM1026 supports Packet Error
Checking (PEC), its use is optional. The PEC byte is
calculated using CRC-8. The Frame Check Sequence
(FCS) conforms to CRC-8 by the polynomial:-
C(x) = x8 + x2 + x1 + 1
Consult SMBus 1.1 specification for more information.
MEASUREMENT INPUTS
The ADM1026 has 17 external analog measurement pins,
which can be configured to perform various functions. It
also measures two supply voltages, 3.3V MAIN and 3.3V
STBY, and the internal chip temperature.
Pins 25 and 26 are dedicated to remote temperature mea-
surement, whilst pins 27 and 28 can be configured as ana-
log inputs with a range of 0 to +2.5V or as inputs for a
second remote temperature sensor.
Pins 29 to 33 are dedicated to measuring VBAT, +5V,
-12V, +12V supplies and the processor core voltage VCCP.
The remaining analog inputs, pins 34 to 41 are general-
purpose analog inputs with a range of 0 to +2.5V (pins 34
and 35) or 0 to +3V (pins 36 to 41).
A TO D CONVERTER
These inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. This has a
resolution of 8 bits. The basic input range is zero to
+2.5V, which is the input range of AIN6 to AIN9, but five of
the inputs have built-in attenuators to allow measurement
of VBAT, +5V, -12V, +12V and the processor core voltage
VCCP, without any external components. To allow for the
tolerance of these supply voltages, the A to D converter
produces an output of 3/4 full-scale (decimal 192) for the
nominal input voltage, and so has adequate headroom to
cope with overvoltages. Table 2 shows the input ranges of
the analog inputs and output codes of the A to D con-
verter.
When the ADC is running, it samples and converts an ana-
log or local temperature input every 711µs (typical value).
Each input is measured 16 times and the measurements
averaged to reduce noise, so the total conversion time for
each input is 11.38ms.
Measurements on the remote temperature (D1 and D2) in-
puts take 2.13ms. These are also measured 16 times and
averaged, so the total conversion time for a remote tem-
perature input is 34.13ms.
INPUT CIRCUITS
The internal structure for the analog inputs are shown in
Figure 5. Each input circuit consists of an input protec-
tion diode, an attenuator, plus a capacitor to form a first-
order lowpass filter which gives the input immunity to
high frequency noise. The -12V input also has a resistor
connected to the on-chip reference to offset the negative
voltage range so that it is always positive and can be
handled by the ADC. The VBAT input allows the condition
PRELIMINARY TECHNICAL DATA
TABLE 2. A/D OUTPUT CODE VS. VIN
ADM1026
PRELIMINARY TECHNICAL DATA
current drain on the VBAT pin is 105nA typical (for a
maximum VBAT voltage = 4V) so a CR2032 CMOS
battery will function in a system in excess of the expected
10 years. Note that when a measurement is not being
made of VBAT the current drain is reduced to 16nA typical.
Under normal operating conditions, all measurements are
made in a round-robin format, and each measurement
result is actually 16 digitally averaged measurements.
Averaging is not carried out on the VBAT measurement to
reduce measurement time and hence reduce the current
drain from the battery. The VBAT current drain when a
measurement is being made is calculated by: -
I = (VBAT/100k) *(TPULSE/TPERIOD)
For VBAT = 3V;
I = (3/100k) * (711μs/273ms) = 78nA
TPULSE = VBAT measurement time = 711μs typical
TPERIOD = Time to measure all analog inputs = 273ms
typical
SETTING OTHER INPUT RANGES
AIN0 to AIN9 can easily be scaled to voltages other than
2.5V or 3V. If the input voltage range is zero to some
positive voltage, then all that is required is an input at-
tenuator, as shown in Figure 6.
However, when scaling AIN0 to AIN5, it should be noted that
these inputs already have an on-chip attenuator, as their
primary function is to monitor SCSI termination voltages.
This attenuator will load any external attenuator. The in-
put resistance of the on-chip attenuator can be between
100k� and 200k�. For this tolerance not to affect the ac-
curacy, the output resistance of the external attenuator
should be very much lower than this, e.g. 1k� in order to
add not more than 1% to the TUE. Alternatively, the
input can be buffered using an op-amp.
Figure 6. Scaling AIN(0 - 9)
R1/R2 = (Vfs-3.0)/3.0 (for AIN0 to AIN5)
R1/R2 = (Vfs-2.5)/2.5 (for AIN6 to AIN9)
Negative and bipolar input ranges can be accommodated
by using a positive reference voltage to offset the input
voltage range so that it is always positive.
To monitor a negative input voltage, an attenuator can be
used as shown in Figure 7.
Figure 7. Scaling and Offsetting AIN(0 - 9) for Negative In-
puts
This offsets the negative voltage so that the ADC always
sees a positive voltage. R1 and R2 are chosen, so that the
ADC input voltage is zero when the negative input voltage
is at its maximum (most negative) value, i.e.
R1/R2 = |VFS-|/VOS
This is a simple and cheap solution, but the following
point should be noted.Since the input signal is offset but not inverted, the in-
PRELIMINARY TECHNICAL DATA
magnitude of the negative voltage will cause the ADC
code to increase. The maximum negative voltage cor-
responds to zero output from the ADC. This means
that the upper and lower limits will be transposed.For the ADC output to be full-scale when the negative
voltage is zero, VOS must be greater than the full-scale
voltage of the ADC, because VOS is attenuated by R1
and R2. If VOS is equal to or less than the full-scale
voltage of the ADC the input range is bipolar, but not
necessarily symmetrical.
This is only a problem if the ADC output must be full-
scale when the negative voltage is zero.
Symmetrical bipolar input ranges can easily be accommo-
dated by making VOS equal to the full-scale voltage of the
analog input and adding a third resistor to set the positive
full-scale.
Figure 8. Scaling and Offsetting AIN(0 - 9) for Bipolar Inputs
R1/R2 = |VFS-|/VOS
(R3 has no effect as the input voltage at the device pin is
zero when VIN = minus full-scale)
R1/R3 = (VFS+-3.0)/3.0 (for AIN0 to AIN5)
R1/R3 = (VFS+-2.5)/2.5 (for AIN6 to AIN9)
(R2 has no effect as the input voltage at the device pin is
equal to VOS when VIN = plus full-scale).
REFERENCE OUTPUT
The on-chip reference voltage is scaled and buffered at pin
24 to provide a 1.82V or 2.5V reference. This output can
source or sink a load current of 2mA. The reference volt-
age is set to 1.82V if bit 2 of Configuration Register 3
(address 07h) is 0, 2.5V if it is 1. The voltage reference
output can be used to provide a stable reference voltage to
external circuitry such as LDO's.
TEMPERATURE MEASUREMENT SYSTEM
LOCAL TEMPERATURE MEASUREMENT
The ADM1026 contains an on-chip bandgap temperature
sensor, whose output is digitized by the on-chip ADC.
The temperature data is stored in the Local Temperature
Value Register (address 1Fh). As both positive and nega-
tive temperatures can be measured, the temperature data is
stored in two's complement format, as shown in Table 3.
Theoretically, the temperature sensor and ADC can mea-
sure temperatures from -128oC to +127oC with a resolu-
tion of 1oC. However, temperatures below TMIN and above
TMAX are outside the operating temperature range of the
device, so local temperature measurements outside this
range are not possible. Temperature measurement from
-128oC to +127oC is possible using a remote sensor.
REMOTE TEMPERATURE MEASUREMENT
The ADM1026 can measure the temperature of two
remote diode sensors or diode-connected transistors, con-
nected to pins 25 and 26 or 27 and 28.
Pins 25 and 26 are a dedicated temperature input channel.
Pins 27 and 28 can be configured to measure a diode sen-
sor by clearing bit 3 of Configuration Register 1 (address
00h) to 0. If this bit is 1 then pins 27 and 28 are AIN8 and
AIN9.
The forward voltage of a diode or diode-connected tran-
sistor, operated at a constant current, exhibits a negative
temperature coefficient of about -2mV/oC.Unfortunately,
the absolute value of Vbe, varies from device to device, and
individual calibration is required to null this out, so the
technique is unsuitable for mass-production.
ADM1026
PRELIMINARY TECHNICAL DATA
The technique used in the ADM1026 is to measure the
change in Vbe when the device is operated at two different
currents.
This is given by:
ΔVbe = KT/q x ln(N)
where:
K is Boltzmann’s constant
q is charge on the carrier
T is absolute temperature in Kelvins
N is ratio of the two currents
Figure 9 shows the input signal conditioning used to mea-
sure the output of a remote temperature sensor. This fig-
ure shows the external sensor as a substrate transistor,
provided for temperature monitoring on some micropro-
cessors, but it could equally well be a discrete transistor
such as a 2N3904.
If a discrete transistor is used, the collector will not be
grounded, and should be linked to the base. If a PNP
transistor is used the base is connected to the D- input and
the emitter to the D+ input. If an NPN transistor is used,
the emitter is connected to the D- input and the base to
the D+ input.
TABLE 3. TEMPERATURE DATA FORMAT
TemperatureDigital Output
-128 °C1000 0000
-125 °C1000 0011
-100 °C1001 1100
-75 °C1011 0101
-50 °C1100 1110
-25 °C1110 0111
-10 oC11110110
0 °C0000 0000
+10 °C0000 1010
+25 °C0001 1001
+50 °C0011 0010
+75 °C0100 1011
+100 °C0110 0100
+125 °C0111 1101
+127 °C0111 1111
To prevent ground noise interfering with the measure-
ment, the more negative terminal of the sensor is not ref-
erenced to ground, but is biased above ground by an
and to a chopper-stabilized amplifier that performs the
functions of amplification and rectification of the wave-
form to produce a DC voltage proportional to ΔVbe. This
voltage is measured by the ADC to give a temperature
output in 8-bit two’s complement format. To further re-
duce the effects of noise, digital filtering is performed by
averaging the results of 16 measurement cycles. A remote
temperature measurement takes nominally 2.14ms.
The results of external temperature measurements are
stored in 8 bit, twos-complement format, as illustrated in
Table 3.
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments, and
care must be taken to protect the analog inputs from
noise, particularly when measuring the very small voltages
from a remote diode sensor. The following precautions
should be taken:Place the ADM1026 as close as possible to the remote
sensing diode. Provided that the worst noise sources
such as clock generators, data/address buses and CRTs
are avoided, this distance can be 4 to 8 inches.Route the D+ and D- tracks close together, in parallel,
with grounded guard tracks on each side. Provide a
ground plane under the tracks if possible.Use wide tracks to minimize inductance and reduce
noise pickup. 10 mil track minimum width and spacing
is recommended.
Figure 10. Arrangement of Signal TracksTry to minimize the number of copper/solder joints,
which can cause thermocouple effects. Where copper/
solder joints are used, make sure that they are in both
the D+ and D- path and at the same temperature.
Thermocouple effects should not be a major problem asoC corresponds to about 240µV, and thermocouple
voltages are about 3µV/oC of temperature difference.
Unless there are two thermocouples with a big tempera-
ture differential between them, thermocouple voltages
should be much less than 200μV.Place a 0.1µF bypass capacitor close to the ADM1026.If the distance to the remote sensor is more than 8
inches, the use of twisted pair cable is recommended.
This will work up to about 6 to 12 feet.
PRELIMINARY TECHNICAL DATA
of the shield unconnected to avoid ground loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can
affect the measurement. When using long cables, the filter
capacitor may be reduced or removed.
Cable resistance can also introduce errors. 1� series resis-
tance introduces about 0.5oC error.
LIMIT VALUES
Limit values for analog measurements are stored in the
appropriate limit registers. In the case of voltage measure-
ments, high and low limits can be stored so that an inter-
rupt request will be generated if the measured value goes
above or below acceptable values. In the case of tempera-
ture, a Hot Temperature or High Limit can be pro-
grammed, and a Hot Temperature Hysteresis or Low
Limit, which will usually be some degrees lower. This
can be useful as it allows the system to be shut down when
the hot limit is exceeded, and re-started automatically
when it has cooled down to a safe temperature.
ANALOG MONITORING CYCLE TIME
The analog monitoring cycle begins when a one is written to
the Start Bit (bit 0), and a zero to the ���_Clear Bit (bit 2)
of the Configuration Register. ���_Enable (Bit 1) should
be set to one to enable the ��� output. The ADC measures
each analog input in turn, starting with remote temperature
channel 1 and ending with local temperature. As each mea-
surement is completed the result is automatically stored in
the appropriate value register. This "round-robin" monitor-
ing cycle continues until it is disabled by writing a 0 to bit 0
of the Configuration Register.
As the ADC will normally be left to free-run in this man-
ner, the time taken to monitor all the analog inputs will
normally not be of interest, as the most recently measured
value of any input can be read out at any time.
For applications where the monitoring cycle time is im-
portant, it can easily be calculated.
The total number of channels measured is:
5 dedicated supply voltage inputs
10 general purpose analog inputs
3.3VMAIN
3.3VSTBY
Local temperature
2 remote temperature
Pins 28 and 27 are measured both as analog inputs AIN8/
AIN9 and as remote temperature input D2+/D2-, irre-
spective of which configuration is selected for these pins.
If pins 28 and 27 are configured as AIN8/AIN9, the mea-
surements for these channels are stored in registers 27h and
29h and the invalid temperature measurement is discarded.
On the other hand, if pins 28 and 27 are configured as
D2+/D2-, the temperature measurement is stored in regis-
is measured 16 times and averaged to reduce noise.
The total monitoring cycle time for voltage and tempera-
ture inputs is therefore nominally:
(18 � 16 � 0.711) + (2 � 16 � 2.13) = 273ms
The ADC uses the internal 22.5kHz clock, which has a
tolerance of ±6%, so the worst case monitoring cycle time
is 290ms.
The fan speed measurement uses a completely separate
monitoring loop, as described later.
INPUT SAFETY
Scaling of the analog inputs is performed on chip, so ex-
ternal attenuators are normally not required. However,
since the power supply voltages will appear directly at the
pins, its is advisable to add small external resistors (e.g.
500Ω) in series with the supply traces to the chip to pre-
vent damaging the traces or power supplies should an acci-
dental short such as a probe connect two power supplies
together.
As the resistors will form part of the input attenuators,
they will affect the accuracy of the analog measurement if
their value is too high.
The worst such accident would be connecting -12V to
+12V - a total of 24V difference, with the series resistors
this would draw a maximum current of approx. 24mA.
REFERENCE OUTPUT
The ADM1026 has a buffered reference voltage output
(pin 24), which can be programmed to 1.82V or 2.5V by
clearing or setting bit 2 of Configuration Register 3 (ad-
dress 07h).
ANALOG OUTPUT
The ADM1026 has a single analog output from an un-
signed 8 bit DAC which produces 0 - 2.5V (independent
of the reference voltage setting). The input data for this
DAC is contained in the DAC Control register (address
04h) The DAC Control Register defaults to FFh during
power-on reset, which produces maximum fan speed. The
analog output may be amplified and buffered with exter-
nal circuitry such as an op-amp and transistor to provide
fan speed control. During automatic fan speed control, de-
scribed later, the four MSBs of this register set the mini-
mum fan speed.
Suitable fan drive circuits are given in Figures 11a to 11e.
When using any of these circuits, the following points
should be noted:All of these circuits will provide an output range from
zero to almost +12V, apart from Figure 11a which
loses the base-emitter voltage drop of Q1 due to the
emitter-follower configuration.To amplify the 2.5V range of the analog output up to
12V, the gain of these circuits needs to be around 4.8.Care must be taken when choosing the op-amp to en-
ADM1026
PRELIMINARY TECHNICAL DATA
Figure 11a.Fan Drive Circuit with Op-Amp and Emitter—
Follower
Figure 11b. Fan Drive Circuit with Op-Amp and PNP Tran-
sistor
Figure 11d. Discrete Fan Drive Circuit with P-Channel
MOSFET, SIngle Supply
Figure 11e.Discrete Fan Drive Circuit with P-Channel
MOSFET, Dual Supply
PRELIMINARY TECHNICAL DATA
sure that its input common-mode range and output
voltage swing are suitable.The op-amp may be powered from the +12V rail alone
or from ±12V. If it is powered from +12V then the in-
put common-mode range should include ground to ac-
commodate the minimum output voltage of the DAC,
and the output voltage should swing below 0.6V to en-
sure that the transistor can be turned fully off.If the op-amp is powered from -12V then precautions
such as a clamp diode to ground may be needed to pre-
vent the base-emitter junction of the output transistor
being reverse-biased in the unlikely event that the out-
put of the op-amp should swing negative for any rea-
son.In all these circuits, the output transistor must have an
ICMAX greater than the maximum fan current, and be
capable of dissipating power due to the voltage
dropped across it when the fan is not operating at full-
speed.If the fan motor produces a large back e.m.f when
switched off, it may be necessary to add clamp diodes
to protect the output transistors in the event that the
output goes from full-scale to zero very quickly.
PWM OUTPUT
Fan speed may also be controlled using pulse-width
modulation (PWM). The PWM output (pin 18) produces
a pulsed output with a frequency of approximately 75Hz
and a duty-cycle defined by the contents of the PWM
Control Register (address 05h). During automatic fan
speed control, described below, the four MSBs of this
register set the minimum fan speed.
The open-drain PWM output must be amplified and
buffered to drive the fans. The PWM output is intended to
be used with an NMOS driver, but may be inverted by
setting bit 1 of Test Register 1(address 14h) if using
PMOS drivers. Figure 11f shows how a fan may be driven
under PWM control using an N-channel MOSFET.
AUTOMATIC FAN SPEED CONTROL
The ADM1026 offers a simple method of controlling fan
speed according to temperature without intervention from
the host processor.
To enable automatic fan speed control, monitoring must
be enabled by setting Bit 0 of Configuration Register 1
(address 00h).
Automatic fan speed control can be applied to the DAC
output, the PWM output, or both, by setting bit 5 and/or
6 of Configuration Register 1.
The TMIN registers (addresses 10h to 12h) contain mini-
mum temperature values for the three temperature chan-
nels (on-chip sensor and two remote diodes). This is the
temperature at which a fan will start to operate when the
temperature sensed by the controlling sensor exceeds
TMIN. TMIN can be the same or different for all three chan-
In Automatic Fan Speed Control Mode, the four MSBs of
the DAC Control Register (address 04h) and PWM
Control Register (address 05h) set the minimum values
for the DAC and PWM outputs. Note: If both DAC
Control and PWM Control is enabled (bits 5, 6 of
Configuration Register 1 = 1), the four MSBs of the DAC
Control Register (address 04h) define the minimum fan
speed values for both the DAC and PWM outputs. The
value in the PWM Control Register (address 05h) has no
effect.
Minimum DAC Code DACMIN = 16 � D
(DAC output voltage = 2.5 � Code/256)
Minimum PWM Duty-Cycle PWMMIN = 6.67 � D
where D is the decimal equivalent of bits 7 to 4 of the reg-
ister.
When the temperature measured by any of the sensors ex-
ceeds the corresponding TMIN, the fan is spun up for two
seconds with the fan drive set to maximum (full-scale
from the DAC or 100% PWM duty-cycle. The fan speed
is then set to the minimum as previously defined. As the
temperature increases, the fan drive will increase until the
temperature reaches TMIN +20oC.
The fan drive at any temperature up to 20oC above TMIN is
given by:
PWM = PWMMIN + (100 - PWMMIN) � (TACTUAL - TMIN)/20)
DAC = DACMIN + (240 - DACMIN) � (TACTUAL - TMIN)/20)
For simplicity of the automatic fan speed algorithm, the
DAC code increases linearly up to 240, not its full-scale
of 255. However, when the temperature exceeds TMIN
+20oC, the DAC output will jump to full-scale.
PWM
OUTPUT
MIN
TEMPERATURE
TMINTMIN + 20o
100%
TMIN - 4o
Figure 12a. Automatic PWM Fan Control Transfer Function
ADM1026
PRELIMINARY TECHNICAL DATA
DAC
OUTPUT
MIN
TEMPERATURE
TMINTMIN + 20o
TMIN - 4o
Figure 12b. Automatic DAC Fan Control Transfer Function
To ensure that the maximum cooling capacity is always
available, the fan drive is always set by the sensor channel
demanding the highest fan speed.
If the temperature falls, the fan will not turn off until the
temperature measured by all three temperature sensors has
fallen to their corresponding TMIN – 4oC. This prevents
the fan from cycling on and off continuously when the
temperature is close to TMIN.
Whenever a fan starts or stops during automatic fan speed
control, a one-off interrupt is generated at the ��� out-
put. This is described in more detail in the section on the
ADM1026 Interrupt Structure.
FAN INPUTS
Pins 3 to 6 and 9 to 12 may be configured as fan speed
measuring inputs by clearing the corresponding bit(s) of
Configuration Register 2 (address 01h) or as general-pur-
pose logic inputs/outputs by setting bits in this register.
The power-on default value for this register is 00h, which
means all the inputs are set for fan speed measurement.
Signal conditioning in the ADM1026 accommodates the
slow rise and fall times typical of fan tachometer outputs.
The Fan Tach inputs have internal 10kΩ pullup resistors
to 3.3VSTBY. In the event that these inputs are supplied
from fan outputs which exceed the supply, either resistive
attenuation of the fan signal or diode clamping must be
included to keep inputs within an acceptable range.
Figures 13a to 13d show circuits for most common fan
tacho outputs.
If the fan tacho output is open drain or has a resistive pullup
to VCC then it can be connected directly to the fan input, as
shown in Figure 13a.
If the fan output has a resistive pullup to +12V (or other
voltage greater than 3.3VSTBY) then the fan output can
be clamped with a zener diode, as shown in Figure 13b.
The zener voltage should be chosen so that it is greater
than VIH but less than 3.3VSTBY, allowing for the voltage
tolerance of the zener.
Figure 13b. Fan with Tach. Pullup to Voltage >VCC e.g. 12V)
Clamped with Zener Diode
If the fan has a strong pullup (less than 1k�) to +12V, or
a totem-pole output, then a series resistor can be added to
limit the zener current, as shown in Figure 13c. Alterna-
tively, a resistive attenuator may be used, as shown in
Figure 13d.
R1 and R2 should be chosen such that:
2V < VPULLUP x R2/(RPULLUP + R1 + R2) < 3.3VSTBY
Figure 13c. Fan with Strong Tach. Pullup to >VCC or Totem-
Pole Output, Clamped with Zener and Resistor
Figure 13d. Fan with Strong Tach. Pullup to >VCC or Totem-
Pole Output, Attenuated with R1/R2
FAN SPEED MEASUREMENT
The fan counter does not count the fan tacho output pulses
directly, because the fan speed may be less than 1000 RPM
and it would take several seconds to accumulate a reason-
ably large and accurate count. Instead, the period of the fan
revolution is measured by gating an on-chip 22.5kHz oscil-
PRELIMINARY TECHNICAL DATA
Figure 14. Fan Speed Measurement
The monitoring cycle begins when a one is written to the
Monitor Bit (bit 0 of Configuration Register 1). The
���_Enable (Bit 1) should be set to one to enable the
��� output.
Speed measurement of the Fan 0 channel is initialized on
the first rising edge of the fan tach pulse after Start goes
low, and oscillator pulses are actually counted from the
second rising tach edge to the fourth rising edge. The
measurement then switches to Fan 1. Here again, the
measurement is initialized on the first tach pulse rising
edge after the Fan 0 measurement finishes and oscillator
pulses are counted from the second rising edge to the
fourth rising edge. This is repeated for the other six fan
channels.
To accommodate fans of different speed and/or different
numbers of output pulses per revolution, a pre-scaler (di-
visor) of 1, 2, 4 or 8 may be added before the counter.
Divisor values for Fans 0 to 3 are contained in the Fan 0-
3 Divisor Register (address 02h) and those for Fans 4 to 7
in the Fan 4-7 Divisor Register (address 03h). The de-
fault value is 2, which gives a count of 153 for a fan run-
ning at 4400 RPM producing two output pulses per
revolution.
The count is calculated by the equation:
Count = (22.5 x 103x 60) /(RPM x Divisor)
For constant speed fans, fan failure is normally considered
to have occurred when the speed drops below 70% of
nominal, which would correspond to a count of 219. Full-
scale (255) would be reached if the fan speed fell to 60%
of its nominal value. For temperature-controlled variable
speed fans the situation will be different.
Table 4 shows the relationship between fan speed and
time per revolution at 60%, 70% and 100% of nominal
RPM for fan speeds of 1100, 2200, 4400 and 8800 RPM,
and the divisor that would be used for each of these fans,
based on two tacho pulses per revolution.
TABLE 4. FAN SPEEDS AND DIVISORS
DivisorNominalTime per70%Time per60%Time per
RPMrevRPMrev (70%)RPMrev (60%)
(ms)(ms)(ms)
÷ 4220027.27154038.96132045.45
÷ 8110054.5477077.9266090.9
LIMIT VALUES
Fans generally do not overspeed if run from the correct
voltage, so the failure condition of interest is underspeed
due to electrical or mechanical failure. For this reason
only low-speed limits are programmed into the limit reg-
isters for the fans. It should be noted that, since fan period
rather than speed is being measured, a fan failure interrupt
will occur when the measurement exceeds the limit value.
FAN MONITORING CYCLE TIME
The fan speeds are measured in sequence from 0 to 7.
The monitoring cycle time depends on the fan speed, the
number of tacho output pulses per revolution and the
number of fans being monitored.
If a fan is stopped or running so slowly that the fan speed
counter reaches 255 before the second tach pulse after ini-
tialization, or before the fourth tach pulse during mea-
surement, the measurement will be terminated. This will
also occur if an input is configured as GPIO instead of
fan. Any channels so connected will time out after 255
clock pulses.
The worst-case measurement time for a fan-configured
channel occurs when the counter reaches 254 from start to
the 2nd tach pulse and reaches 255 after the second tach
pulse. Taking into account the tolerance of the oscillator
frequency, the worst-case measurement time is:
509 � D � 0.047 milliseconds
where:
509 is the total number of clock pulses.
D is the divisor, 1,2, 4 or 8.
0.047 is the worst-case oscillator period in ms.
The worst-case fan monitoring cycle time is the sum of
the worst case measurement time for each fan.
Although the fan monitoring cycle and the analog input
monitoring cycle are started together, they are not
synchronised in any other way.
FAN MANUFACTURERS
Manufacturers of cooling fans with tachometer outputs are
listed below:
NMB Tech
9730 Independence Ave.
Chatsworth, California 91311
818-341-8207
ADM1026
PRELIMINARY TECHNICAL DATA
ModelFrame SizeAirflow
CFM
2408NL2.36 in sq. X 0.79 in (60mm sq. X 20mm)9-16
2410ML2.36 in sq. X 0.98 in (60mm sq. X 25mm)14-25
3108NL3.15 in sq. X 0.79 in (80mm sq. X 20mm)25-42
3110KL3.15 in sq. X 0.98 in (80mm sq. X 25mm)25-40
Mechatronis Inc.
P.O. Box 20
Mercer Island, WA 98040
Models - Various sizes available with tach output option.
Sanyo Denki/Keymarc Electronics
2310 205th, Suite 101
Torrance, CA 90501
Models - 109P Series
CHASSIS INTRUSION INPUT
The Chassis Intrusion input is an active high input in-
tended for detection and signalling of unauthorised tam-
pering with the system. When this input goes high, the
event is latched in bit 6 of Status Register 4 and an inter-
rupt will be generated. The bit will remain set until
cleared by writing a zero to it, so long as battery voltage is
connected to the VBAT input, even if the ADM1026 is pow-
ered off.
The CI input will detect chassis intrusion events even
when the ADM1026 is powered off (provided battery volt-
age is applied to VBAT) but will not immediately generate
an interrupt. Once a chassis intrusion event has been de-
tected and latched, an interrupt will be generated when the
system is powered up.
The actual detection of chassis intrusion is performed by
an external circuit that will detect (for example), when the
cover has been removed. A wide variety of techniques may
be used for the detection, for example:Microswitch that opens or closes when the cover is re
moved.Reed switch operated by magnet fixed to the coverHall-effect switch operated by magnet fixed to the
cover.Phototransistor that detects light when cover is removed.
The Chassis Intrusion input can also be used for other types
of alarm input. Figure 15 shows a temperature alarm circuit
using an AD22105 temperature switch sensor. This pro-
duces a low-going output when the preset temperature is
exceeded, so the output is inverted by Q1 to make it com-
Figure 15. Using the CI Input with a Temperature Sensor
GENERAL-PURPOSE I/O PINS
The ADM1026 has 8 pins that are dedicated to general-
purpose logic input/output (pins 1, 2 and 43 to 48), 8 pins
that can be configured as general-purpose logic pins or fan
speed inputs (pins 3 to 6 and 9 to 12) and one pin that can
be configured as GPIO16 or ����� output (pin 42).
The GPIO/FAN pins are configured as general-purpose
logic pins by setting bits 0 to 7 of Configuration Register
2 (address 01h). Pin 42 is configured as GPIO16 by set-
ting bit 0 of Configuration Register 3, or as ����� out-
put by clearing this bit.
Each GPIO pin has four data bits associated with it, two
bits in one of the GPIO Configuration Registers
(addresses 08h to OBh), one in the GPIO Status Registers
(addresses 24h and 25h), and one in the GPIO Mask
Registers (addresses 1Ch and 1Dh)
Setting a Direction Bit = 1 in one of the GPIO
Configuration Registers makes the corresponding GPIO
pin an output. Clearing the direction bit to 0 makes it an
input.
Setting a Polarity Bit = 1 in one of the GPIO
Configuration Registers makes the corresponding GPIO
pin active high. Clearing the polarity bit to 0 makes it
active low.
When a GPIO pin is configured as an INPUT, the corre-
sponding bit in one of the GPIO status registers is read-
only, and is set when the input is asserted ("asserted" may
be high or low depending on the setting of the Polarity
Bit).
When a GPIO pin is configured as an OUTPUT, the cor-
responding bit in one of the GPIO status registers
becomes read/write. Setting this bit will then assert the
GPIO output. (here again, "asserted" may be high or low
depending on the setting of the polarity bit).
The effect of a GPIO Status Register bit on the ��� out-
put can be masked out by setting the corresponding bit in
one of the GPIO Mask Registers. When the pin is config-
ured as an output, this bit will automatically be masked to
prevent the data written to the status bit from causing an
interrupt, with the exception of GPIO16 which must be
masked manually by setting bit 7 of Mask Register 4.
When configured as inputs, the GPIO pins may be connected
to external interrupt sources such as temperature sensors with
digital output. Another application of the GPIO pins would
PRELIMINARY TECHNICAL DATA
���
FROM FAN SPEED
VALUE AND
LIMIT REGISTERS
VALUE
HIGH LIMIT
GPIO0 TO GPIO7
GPIO8 TO GPIO15
MASKING DATA
FROM SMBUS
MASKING DATA
FROM SMBUS
HIGH LIMIT
LOW LIMIT
VALUE
FROM ANALOG/TEMP.
VALUE AND LIMIT
REGISTERS
MASK DATA FROM
SMBUS (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
MASK DATA FROM
SMBUS (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
ADM1026
PRELIMINARY TECHNICAL DATA
THE ADM1026 INTERRUPT STRUCTURE
The Interrupt Structure of the ADM1026 is shown in Figure
16. Interrupts can come from a number of sources, which
are combined to form a common ��� output. When ���
is asserted, this output pulls low. The ��� pin has an in-
ternal, 100k� pullup resistor.Analog/Temperature Inputs
As each analog measurement value is obtained and stored in
the appropriate value register, the value and the limits from
the corresponding limit registers are fed to the high and low
limit comparators. The result of each comparison (1 = out of
limit, 0 = in limit) is routed to the corresponding bit input of
Interrupt Status Register 1, 2 or 4 via a data demultiplexer,
and used to set that bit high or low as appropriate. Status
bits are self-clearing. If a bit in a status register is set due
to an out-of-limit measurement, it will continue to cause
��� to be asserted as long as it remains set, as described
below. However, if a subsequent measurement is in limit
it will be reset and will not cause ��� to be re-asserted.
Status bits are unaffected by clearing the interrupt.
Interrupt Mask Registers, 1, 2 and 4 have bits correspond-
ing to each of the Interrupt Status Register Bits. Setting
an Interrupt Mask Bit high forces the corresponding Sta-
tus Bit output low, whilst setting an Interrupt Mask Bit
low allows the corresponding Status Bit to be asserted. Af-
ter mask gating, the status bits are all OR'd together to
produce the analog and fan interrupt, which is used to set
a latch. The output of this latch is OR'd with other inter-
rupt sources to produce the ��� output. This will pull
low if any unmasked status bit goes high, i.e. when any
measured value goes out of limit.
When an ��� output due to an out-of-limit analog/temp.
measurement is cleared by one of the methods described
later, the latch is reset. It will not be set again, and����
will not be re-asserted, until the end of the next monitor-
Figure 17. Delay After Clearing INT Before Re-assertion
START OF ANALOG
MONITORING CYCLE
OUT-OF-LIMIT
MEASUREMENT
LOCAL TEMP.
MEASUREMENT
START OF ANALOG
MONITORING CYCLE
LOCAL TEMP.
MEASUREMENT
START OF ANALOG
MONITORING CYCLE
���
CLEARED
���
CLEARED
GPIO
DE-ASSERTED
ing cycle, even if the status bit remains set or a new ana-
log/temp. event occurs. However, interrupts from other
sources such as fan or GPIO can still be asserted. This is
illustrated in Figures 17 and 18.
Status Register 4 also stores inputs from two other inter-
rupt sources, which operate in a different way from the
other status bits. If automatic fan speed control (AFC) is
enabled, bit 4 of status register 4 will be set whenever a
fan starts or stops. This bit causes a one-off ��� output as
shown in Figure 19. It is cleared during the next monitor-
ing cycle and if ��� has been cleared it will not cause
��� to be re-asserted.
���
INT CLEARED BY STATUS REG 1 READ,
BIT 2 OF CONFIG.REG. 1 SET, OR ARA
FAN ON
FAN OFF
Figure 19. Assertion Of INT Due To AFC Event
In a similar way, a change of state at the ����� output
(described in more detail later), sets bit 3 of Status Regis-
ter 4 and causes a one-off ��� output. A change of state
at the ����� output also causes bit 0 of Status Register
1, bit 1 of Status Register 1, or bit 0 of Status Register 4
to be set, depending on which temperature channel caused
the ����� event. This bit will be reset during the next
monitoring cycle, provided the temperature channel is
within the normal high and low limits.Fan Inputs
Fan inputs generate interrupts in a similar way to analog/
temp. inputs, but as the analog/temp. inputs and fan inputs
have different monitoring cycles, they have separate inter-
PRELIMINARY TECHNICAL DATA
rupt circuits. As the speed of each fan is measured, the
output of the fan speed counter is stored in a value regis-
ter. The result is compared to the fan speed limit and used
to set or clear a bit in Status Register 3. In this case the
fan is only monitored for under-speed (fan counter > fan
speed limit). Mask Register 3 is used to mask fan inter-
rupts. After mask gating, the fan status bits are OR'd to-
gether and used to set a latch, whose output is OR'd with
other interrupt sources to produce the ��� output.
Like the analog/temp. interrupt, an ��� output caused by
an out-of-limit fan speed measurement, once cleared, will
not be re-asserted until the end of the next monitoring
cycle, although other interrupt sources may cause ��� to
be asserted.GPIO and CI Pins
When GPIO pins are configured as inputs, asserting a
GPIO input (high or low, depending on polarity) sets the
corresponding GPIO status bit in Status Registers 5 and 6
or bit 7 of Status Register 4 (GPIO16). A chassis intru-
sion event sets bit 6 of Status Register 4.
The GPIO and CI status bits, after mask gating, are OR'd
together and OR'd with other interrupt sources to produce
the ��� output. GPIO and CI interrupts are not latched
and cannot be cleared by normal interrupt clearing. They
can only be cleared by masking the status bits or by re-
moving the source of the interrupt.
ENABLING AND CLEARING INTERRUPTS
The ��� output is enabled when Bit 1 of Configuration Reg-
ister 1 (���_Enable) is high, and Bit 2 (���_Clear) is low.
��� may be cleared if:Status Register 1 is read. Ideally, if polling the Status
Registers trying to identify interrupt sources, Status
Register 1 should be polled last, since a read of Status
Register 1 clears all the other Interrupt Status
Registers.the ADM1026 receives the Alert Response Address
(0001 100) over the SMBus.bit 2 of Configuration Register 1 is set.
BIDIRECTIONAL������ PIN
The ADM1026 has a second interrupt pin
(GPIO16������, pin 42) that responds only to thermal
events, e.g. if any of the three temperature sensors exceeds
its ����� temperature limit. This output is enabled by
setting bit 4 of Configuration Register 1 (Reg.00h).
Three thermal limit registers are provided for the three
temperature sensors at addresses 0Dh to 0Fh. These regis-
ters are dedicated to the ����� output and none of the
other limit registers have any effect on the ����� out-
put.
If any of the temperature inputs exceeds the corresponding
limit, ����� will be asserted (low) and the DAC and
the temperature is close to the limit, a fixed hysteresis ofoC is provided. ����� will only be de-asserted when
the measured temperature of all three sensors is 5oC below
the limit.
Whenever the ����� output changes, ��� will be as-
serted, as shown in Figure 20. However, this is edge-trig-
gered, so if ��� is subsequently cleared by one of the
methods previously described, it will not be re-asserted,
even if ����� remains asserted. ����� will only
cause ��� to be asserted again when it changes state.
Note that the ����� pin is bidirectional, so �����
may be pulled low externally as an input. This will cause
the PWM and DAC outputs to go to full-scale until
����� is returned high again.
THERM LIMIT
THERM LIMIT -5oC
�����
���
TEMPERATURE
INT CLEARED BY STATUS REG 1 READ,
BIT 2 OF CONFIG.REG. 1 SET, OR ARA
RESET INPUT AND OUTPUTS
The ADM1026 has two active-low, power-on reset out-
puts, ��������� and ���������. These operate as
follows:
��������� monitors 3.3V STBY. At power-up
��������� will be asserted (pulled low) until 180ms
after 3.3VSTBY rises above the reset threshold.
��������� monitors 3.3V MAIN. At power-up
��������� will be asserted (pulled low) until 180ms
after 3.3V MAIN rises above the reset threshold.
If 3.3V MAIN rises with or before DVCC, ���������
will remain asserted until 180ms after ��������� is
negated.�����������can also function as a ����� in-
put. Pulling this pin low will reset the system to power-on
defaults.
Figure 20. Assertion Of ��� Due To ����� Event
ADM1026
PRELIMINARY TECHNICAL DATA
mated Test Equipment (ATE) board level connectivity
testing. This allows the functionality of all digital inputs
to be tested in a simple manner and any pins that are non-
functional or shorted together to be identified. The struc-
ture of the NAND tree is shown in Figure 22. The device
is placed into NAND Tree Test Mode by powering up
with pin 25 held high. This pin is sampled automatically
after power-up and if it is connected high, then the
NAND test mode is invoked.
Figure 22. NAND Tree
The NAND tree test may be carried out in one of two ways.
1. Start with all inputs low and take them high in turn,
starting with the input nearest to NTEST_OUT
(GPIO16/�����) and working back up the tree to the
input furthest from NTESTOUT (INT). This should
give the characteristic output pattern shown in Figure 23,
with NTESTOUT toggling each time an input is taken
high.
Figure 23. NAND Tree Test Taking Inputs High In Turn
1. Start with all inputs high and take them low in turn,
starting with the input furthest from NTEST_OUT
(INT) and working down the tree to the input nearest to
NTEST_OUT (GPIO16/�����). This should give a
similar output pattern to Figure 24.
Notes:When generating test waveforms, a typical propagation
delay of 500 ns through the NAND tree should be al-
lowed for.If any of the inputs shown in Figure 22 are unused,
they should not be connected direct to ground, but via
a resistor such as 10k�. This will allow the ATE (Au-
tomatic Test Equipment) to drive every input high so
that the NAND tree test can be properly carried out.
PRELIMINARY TECHNICAL DATA
Figure 24. NAND Tree Test taking Inputs Low In Turn
In the event of an input being non-functional(stuck high
or low) or two inputs shorted together, the output pattern
will be different. Some examples are given in Figures 25
to 27.
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
FAN0
FAN1
NTESTOUT
Figure 25. NAND Tree Test With GPIO11 Stuck Low
Figure 25 shows the effect of one input being stuck low.
The output pattern is normal until the stuck input is
reached. Because that input is permanently low, neither it
nor any inputs further up the tree can have any effect on
the output.
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
FAN0
FAN1
NTESTOUT
Figure 26. NAND Tree Test With One Input Stuck High
Figure 26 shows the effect of one input being stuck high.
Taking GPIO12 high should take the output high. How-
ever, the next input up the tree, GPIO11, is already high,
so the output immediately goes low again, causing a miss-
ing pulse in the output pattern.
