ADC12DL040CIVS/NOPB ,Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter 64-TQFP -40 to 85FEATURES DESCRIPTIONThe ADC12DL040 is a dual, low power monolithic23• Single +3.0V Supply Operation ..
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ADC12DL040CIVS/NOPB
Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter 64-TQFP -40 to 85
ADC12DL040
www.ti.com SNAS250D –FEBRUARY 2005–REVISED APRIL 2013
ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter
Checkfor Samples: ADC12DL040
1FEATURES DESCRIPTIONThe ADC12DL040isa dual, low power monolithic
23• Single +3.0V Supply Operation CMOS analog-to-digital converter capable of
• Internal Sample-and-Hold converting analog input signals into 12-bit digital
Internal Reference wordsat 40 Megasamples per second (MSPS). This
converter usesa differential, pipeline architecture with
• Outputs 2.4Vto 3.6V Compatible digital error correction and an on-chip sample-and-
• Power Down Mode hold circuit to minimize power consumption while
• Duty Cycle Stabilizer providing excellent dynamic performance anda 250
MHz Full Power Bandwidth. Operating ona single
• Multiplexed Output Mode +3.0V power supply, the ADC12DL040 achieves 11.1
effective bitsat nyquist and consumes just 210 mW
APPLICATIONS at 40 MSPS, including the reference current. The
• Ultrasound and Imaging Power Down feature reduces power consumptionto mW.
• Instrumentation Communications Receivers The differential inputs providea full scale differential
input swing equalto2 times VREF with the possibility
• Sonar/Radar ofa single-ended input. Full useof the differential
• xDSL inputis recommended for optimum performance. The
• Cable Modems digital outputs from the two ADC's are available ona
single multiplexed 12-bit busor on separate buses.
• DSP Front EndsDuty cycle stabilization and output data format are
selectable usinga quad state function pin. The output
KEY SPECIFICATIONS data canbe setfor offset binaryor two's complement.
• Resolution12 Bits To ease interfacing to lower voltage systems, the
• DNL ±0.3 LSB (typ) digital output driver power pinsof the ADC12DL040
• SNR (fIN=10 MHz)69 dB (typ) canbe connectedtoa separate supply voltagein the
rangeof 2.4Vto the analog supply voltage.
• SFDR (fIN=10 MHz)85 dB (typ) Data Latency7 Clock Cycles This deviceis availablein the 64-lead TQFP package
and will operate over the industrial temperature range
• Power Consumption of −40°Cto +85°C. An evaluation boardis available
(typ) to ease the evaluation process.
(typ)
