AD9937KCP ,CCD Signal Processor with Precision Timing⑩ GeneratorOVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Timing Parameters . . . . . . . ..
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AD9937KCP
CCD Signal Processor with Precision Timing⑩ Generator
REV.0
CCD Signal Processor with
Precision Timing™ Generator
FEATURES
12 MSPS Correlated Double Sampler (CDS)
10-Bit 12 MHz A/D Converter
No Missing Codes Guaranteed
6 dB to 40 dB Variable Gain Amplifier (VGA)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Generator
Precision Timing Core with 1.7 ns Resolution
On-Chip: 6-Channel Horizontal and 1-Channel RS Drivers
4-Phase Vertical Transfer Clocks
Electronic and Mechanical Shutter Modes
On-Chip Sync Generator with External Sync Option
APPLICATIONS
Digital Still Cameras
Industrial Imaging
FUNCTIONAL BLOCK DIAGRAM
H1 A–D
H2 A, B
V1 A/B
V3 A/B
TG1A
TG1B
TG3A
TG3B
VCLK
VCKM
DOUT
REFTREFBOFDHDVD
SLDSCKSDA
GENERAL DESCRIPTIONThe AD9937 is a highly integrated CCD signal processor. It
includes a complete analog front end with A/D conversion,
combined with a full-function programmable timing generator.
A Precision Timing core allows adjustment of high speed clocks
with 1.7ns resolution at 12MHz operation.
The AD9937 is specified at pixel rates of up to 12MHz. The
analog front end includes black level clamping, CDS, VGA, and
a 10-bit A/D converter. The timing generator provides all the
necessary CCD clocks: RS, H-clocks, V-clocks, sensor gate pulses,
and substrate charge reset pulse. Operation is programmed using a
3-wire serial interface.
The AD9937 is packaged in a 56-lead LFCSP and specified over
an operating temperature range of –25°C to +85°C.
AD9937
TABLE OF CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . .1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . .3
ANALOG SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . .4
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . .5
ABSOLUTION MAXIMUM RATINGS . . . . . . . . . . . . . . .5
PACKAGE THERMAL CHARACTERISTICS . . . . . . . . .5
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . .6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .6
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . .7
Peak Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Total Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . .7
EQUIVALENT CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . .7
TYPICAL PERFORMANCE CHARACTERISTICS . . . . .8
REGISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . .18
Control Register Serial Interface . . . . . . . . . . . . . . . . . . .18
System and Mode Register Serial Interface . . . . . . . . . . .18
Page/Burst Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Random Access Option . . . . . . . . . . . . . . . . . . . . . . . . . .18
Internal Power-On Reset Circuitry . . . . . . . . . . . . . . . . . .19
VD Synchronous and Asynchronous Register Operation .19
Asynchronous Register Operation . . . . . . . . . . . . . . . . . .19
VD Synchronous Register Operation . . . . . . . . . . . . . . . .19
SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
ANALOG FRONT END DESCRIPTION AND
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . .21
PRECISION TIMING HIGH SPEED TIMING
GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
High Speed Clock Programmability . . . . . . . . . . . . . . . . .22
H-Driver and RS Outputs . . . . . . . . . . . . . . . . . . . . . . . .22
MASTER AND SLAVE MODE OPERATION . . . . . . . . .25
HORIZONTAL AND VERTICAL TIMING . . . . . . . . . . .25
Individual HMASK Sequence . . . . . . . . . . . . . . . . . . . . .25
Individual PBLK Sequences . . . . . . . . . . . . . . . . . . . . . .25
Controlling CLPOB Clamp Pulse Timing . . . . . . . . . . . .28
Vertical Sensor Transfer Gate Timing . . . . . . . . . . . . . . .29
SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . .29
Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .29
High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . .29
Controlling LM Pulse Timing . . . . . . . . . . . . . . . . . . . . .31
SPECIAL HORIZONTAL PATTERN TIMING . . . . . . . .32
MASKING H1 AND H2 OUTPUTS . . . . . . . . . . . . . . . . .33
Horizontal Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Vertical Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
VERTICAL TIMING GENERATION . . . . . . . . . . . . . . .35
CCD REGIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
POWER-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
STANDBY SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . .40
POWER-DOWN SEQUENCE . . . . . . . . . . . . . . . . . . . . . .41
CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . .42
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .44
TABLESTable I. Control Register Map . . . . . . . . . . . . . . . . . . . . . . . .9
Table II. VTP Sequence System Register Map . . . . . . . . . .10
Table III. H/LM System Register Map . . . . . . . . . . . . . . . .12
Table IV. Shutter System Register Map . . . . . . . . . . . . . . . .13
Table V. Mode_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table VI. Mode_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table VII. Serial Interface Registers . . . . . . . . . . . . . . . . . .18
Table VIII. RS, H1, SHP, SHD, and DOUTPHASE
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table IX. Precision Timing Edge Locations for RS, H1,
SHP, SHD, and DOUTPHASE . . . . . . . . . . . . . . . . . . . . .23
Table X. HD and VD Registers . . . . . . . . . . . . . . . . . . . . . .25
Table XI. PBLK Registers . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table XII. CLPOB Registers . . . . . . . . . . . . . . . . . . . . . . . .28
Table XIII. TG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table XIV. OFD Registers . . . . . . . . . . . . . . . . . . . . . . . . .30
Table XV. LM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table XVI. Special H Pattern Registers . . . . . . . . . . . . . . . .33
Table XVII. Sequence Change Positions Registers . . . . . . .35
Table XVIII. Start-Up Polarities . . . . . . . . . . . . . . . . . . . . .39
AD9937–SPECIFICATIONS
(RSVDD = HVDD = 2.7 V to 3.6 V, –25�C to +85�C, unless otherwise noted.)NOTES
DIGITAL SPECIFICATIONSLOGIC OUTPUTS (Except H1(A–D), H2(A, B), and RS)
H-DRIVER OUTPUTS (H1(A–D), H2(A, B))H1 (A–D) and H2 (A, B) LoadsRS Load
AD9937
ANALOG SPECIFICATIONS(AVDD = 3 V, fCLI = 12 MHz, –25�C to +85�C, unless otherwise noted.)BLACK LEVEL CLAMP
A/D CONVERTER
*Input signal characteristics defined as follows:
1V MAX
INPUT
SIGNAL RANGE
100mV MAX
OPTICAL
BLACK PIXEL
500mV TYP
RESET
TRANSIENTSpecifications subject to change without notice.
AD9937
TIMING SPECIFICATIONS(CL = 20 pF, AVDD = DVDD = DRVDD = 3 V, fCLI = 12 MHz, unless otherwise noted.)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9937 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGSTCVDD
HVDD
RSVDD
DVDD
DRVDD
RS Output
H1(A–D), H2(A, B)Output
Digital Outputs
Digital Inputs
SCK, SLD, SDA
VRT, VRB
CCDIN
Junction Temperature
ORDERING GUIDEAFE CLAMP PULSES
DATA OUTPUTS
NOTESParameter is programmable.Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
Specifications subject to change without notice.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance�JA = 24.9°C/W
AD9937
PIN CONFIGURATION
SCKSLDSD
REFB
REFT
CCDIN
AVSS
DRVSS
DRVDD
AVDD
VCKM
TCVDD
TCVSSHDOFDD
VSSV4TG3B V3A/BTG3AV2
TG1B
VCLK
HVDD2
HVSS2
H1DH2BH1B
HVDD1
H1CH2A
HVSS1
H1A
RSVSS
RSVDD
V1A/B
TG1A
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS1NOTESSee Figure 41 for circuit configuration.AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO= Digital Input/Output, P = Power,
NC = No Connection.Schmitt trigger type input.
TERMINOLOGY
Differential Nonlinearity (DNL)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
10-bit resolution indicates that all 1024 codes must be present
over all operating conditions.
Peak NonlinearityPeak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9937 from a true straight
line. The point used as zero scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from
the middle of each particular output code to the true straight line.
The error is then expressed as a percentage of the 2 V ADC full-
scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
Total Output NoiseThe rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
where N is the bit resolution of the ADC. For the AD9937, 1 LSB
is 1.95 mV.
Power Supply Rejection (PSR)The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9937’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
EQUIVALENT CIRCUITSFigure 1. CCDIN
DVDD
DVSSDRVSS
DRVDD
TRISTATEOUT
DATA
DOUTFigure 2. Digital Data Outputs
Figure 3. Digital Inputs
HVDD1, HVDD2,
OR RSVDD
HVSS1, HVSS2,
OR RSVSS
ENABLE
RS,
H1 (A–D),
H2 (A, B)
OUTPUTFigure 4. H1(A–D), H2(A, B), and RS Drivers
AD9937–Typical Performance CharacteristicsTPC 1. Power vs. Sample Rate
TPC 2. Typical DNL Performance
Table I. Control Register MapAD9937
Table II. VTP Sequence System Register Map (Addr 0x14)
Table I. Control Register Map (continued)
Table II. VTP Sequence System Register Map (Addr 0x14) (continued)
AD9937
Table III. H/LM System Register Map (Addr 0x15)HLM_Reg(9)
Table IV. Shutter System Register Map (Addr 0x16)
AD9937
Table V. Mode_A (Addr 0x17)
Table V. Mode_A (Addr 0x17) (continued)
AD9937
Table VI. Mode_B (Addr 0x18)
Table VI. Mode_B (Addr 0x18) (continued)
AD9937
SERIAL INTERFACE TIMINGAll of the internal registers of the AD9937 are accessed through
a 3-wire serial interface. The 3-wire interface consists of a clock
(SCK), serial load (SLD), and serial data (SDA).
The AD9937 has three different register types that are configured
by the 3-wire serial interface pins. As described in Table VII,
the three register types are control registers, system registers,
and mode registers.
Table VII. Serial Interface RegistersVTP Sequence
System Registers
Control Register Serial InterfaceThe control register 3-wire interface timing requirements are
shown in Figure 5. Writing to control registers requires eight bits of
address data followed by 24 bits of configuration data between
each active low period of SLD for each address. The SLD signal
must be kept high for at least one full SCK cycle between suc-
cessive writes to control registers.
System and Mode Register Serial InterfaceThe AD9937 provides two options for writing to system and
mode registers. The Page/Burst write option is used when all the
registers are going to be written to, whereas the Random Access
option is used when only one or a small contiguous sequence of
registers is going to be written to. As shown in Figure 6, the
protocol for writing to system and mode registers requires eight
bits for the address data, 12 bits for the start location, 12 bits
for the end location, and 32 bits for the register data.
Page/Burst OptionThe AD9937 is automatically configured for Page/Burst mode if
both 12-bit STARTADDRESS and ENDADDRESS fields
equal 0. In this configuration, the AD9937 expects all registers
to be written to, therefore all register data must be clocked in
before the SLD pulse is asserted high. The SLD pulse is ignored
until all register data is clocked in. The Page/Burst option is
preferred when initially programming the system and mode
registers at startup.
Random Access OptionWith the Random Access option, the 12-bit STARTADDRESS
and ENDADDRESS fields are typically used when writing to
one system or mode register or a small sequential number of
system or mode registers. In this mode, the address data selects
the system or mode register bank that is going to be accessed,
the 12-bit STARTADDRESS determines the first register to be
accessed, and the 12-bit ENDADDRESS determines the last
register to be accessed. Two examples of Random Access are
provided below (refer to Figure 6).
Example 1: Accessing Only One Register, HLM_Reg(6)HLM_Reg_addr[A7:A0] = 0x15
STARTADDRESS[S11:S0] = 0x0006
ENDADDRESS[E11:E0] = 0x0006
Example 2: Accessing HLM_Reg(2), HLM_Reg(3), and
HLM_Reg(4) SequentiallyHLM_Reg_addr[A7:A0] = 0x15
STARTADDRESS[S11:S0] = 0x0002
ENDADDRESS[E11:E0] = 0x0004
Figure 5. 3-Wire Serial Interface Timing for Control Registers
Figure 6. System and Mode Register Writes
Internal Power-On Reset CircuitryAfter power-on, the AD9937 automatically resets all internal
registers and performs internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes are ignored until the internal reset opera-
tion is completed.
VD Synchronous and Asynchronous Register OperationThere are two types of control registers, VD synchronous and
VD asynchronous, as indicated in the Address column of Table I.
Register writes to synchronous and asynchronous type registers
operate differently as described in the following sections. All
writes to system, Mode_A, and Mode_B registers occur
asynchronously.
Asynchronous Register OperationFor asynchronous register writes, SDA data is stored directly
into the serial register at the rising edge of SLK. As a result,
register operation begins immediately after the register LSB has
been latched in on the rising edge of SCK.
VD Synchronous Register OperationFor VD synchronous type registers, SDA data is temporarily
stored in a buffer register upon completion of clocking in the
last register LSB. This data is held in the temporary buffer
register until the next rising edge of VD is applied. Once the
next rising edge of VD occurs, the buffered register data is
loaded into the serial register, and register operation begins.
See Figure 7.
Control registers at addresses 0x08, 0x09, 0x10, 0x11, and 0x12
are VD synchronous type registers.
Figure 7. VD Synchronous Type Register Writes
AD9937
SYSTEM OVERVIEWFigure 8 shows the typical system block diagram for the AD9937.
The CCD output is processed by the AD9937’s AFE circuitry,
which consists of a CDS, VGA, black level clamp, and A/D
converter. The digitized pixel information is sent to the digital
image processor chip, which performs the postprocessing and
compression. To operate the CCD, all CCD timing parameters
are programmed into the AD9937 from the system micropro-
cessor, through the 3-wire serial interface. From the system
master clock, VCKM provided by the image processor or exter-
nal crystal, the AD9937 generates all of the CCD’s horizontal
and vertical clocks and all internal AFE clocks.
Figure 8. Typical System Block Diagram, Master Mode
The H-drivers for H1(A–D) and H2(A,B), and RS are included
in the AD9937, allowing these clocks to be directly connected
to the CCD. H-drive voltage of up to 3.6 V is supported. An
external V-driver is required for the vertical transfer clocks and
sensor gate pulses.
Figure 9 shows the horizontal and vertical counter dimensions
for the AD9937. All internal horizontal and vertical clocking is
programmed using these dimensions to specify line and pixel
locations.
Figure 9. Horizontal and Vertical Counters
Figure 10. Maximum VD/HD Dimensions
ANALOG FRONT END DESCRIPTION AND OPERATIONThe AD9937 AFE signal processing chain is shown in Figure11.
Each processing step is essential in achieving a high quality image
from the raw CCD pixel data.
DC RestoreTo reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1µF series coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5V to be compatible with the 3V analog supply of
the AD9937.
Correlated Double SamplerThe CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
diagram in Figure 13 illustrates how the two internally gener-
ated CDS clocks, SHP and SHD, are used to sample the
reference level and the data level, respectively, of the CCD
signal. The placement of the SHP and SHD sampling edges is
determined by the setting of the SHPLOC (addr 0x05) and
SHDLOC (addr 0x05) control registers. Placement of these two
clock edges is critical in achieving the best performance from
the CCD.
Figure 11. AFE Block Diagram
AD9937
PRECISION TIMING HIGH SPEED TIMING
GENERATIONThe AD9937 generates flexible high speed timing signals using
the precision timing core. This core is the foundation for gener-
ating the timing used for both the CCD and the AFE: the
reset gate RS, horizontal drivers H1(A–D) and H2(A, B), and
the CDS sample clocks. A unique architecture makes it routine
for the system designer to optimize image quality by providing
precise control over the horizontal CCD readout and the AFE
correlated double sampling.
Timing ResolutionThe precision timing core uses a 13 master clock input
(VCKM) as a reference. This clock should be the same as
the CCD pixel clock frequency. Figure 12 illustrates how
the internal timing core divides the master clock period intosteps or edge positions. Using a 12MHz VCKM fre-
quency, the edge resolution of the precision timing core is
1.7ns. A 24 MHz VCKM frequency can be applied to the
AD9937 where the AD9937 will internally divide the VCKM
frequency by 2. VCKM frequency division by 2 is controlled
by using the VCKM_DIVIDE control (addr 0x04) register.
High Speed Clock ProgrammabilityFigure 13 shows how the high speed clocks RS, H1–H2, SHP, and
SHD are generated. The RS and H1 pulse have positive and nega-
tive edge programmability by using control registers (addr 0x06).
The H2 clock is always the inverse of H1. Table VIII summarizes
the high speed timing registers and the parameters for the high
speed clocks. Each register is six bits wide with the 2 MSB
used to select the quadrant region as outlined in Table IX.
Figure 14 shows the range and default locations of the high
speed clock signals.
H-Driver and RS OutputsIn addition to the programmable timing positions, the AD9937
features on-chip output drivers for the RS and H1–H2 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver current can be adjusted for optimum rise/
fall time into a particular load by using the H1DRV and H2DRV
control registers (addr 0x07). The RS drive current is adjustable
using the RSDRV control register (addr 0x07). The H1DRV,
H2DRV, and RSDRV registers are adjustable in 1.75 mA incre-
ments. All DRV registers have setting of 0 equal to OFF or
three-state, and the maximum setting of 7.
Figure 12. High Speed Clock Resolution from VCKM Master Clock
