AD9887KS-140 ,Dual Interface for Flat Panel DisplaysGENERAL DESCRIPTION2A0DATACKThe AD9887 offers designers the flexibility of a dual analog andHSOUTdi ..
AD9888KS-100 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSPECIFICATIONSD DD1Test AD9888KS-100/-140 AD9888KS-170 AD9888KS-205Parameter Temp Level Min Typ Max ..
AD9888KS-140 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSPECIFICATIONSD DD1Test AD9888KS-100/-140 AD9888KS-170 AD9888KS-205Parameter Temp Level Min Typ Max ..
AD9888KS-170 ,100/140/170/205 MSPS Analog Flat Panel InterfaceSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVEL ..
AD9888KS-205 ,100/140/170/205 MSPS Analog Flat Panel InterfaceGENERAL DESCRIPTION The AD9888’s on-chip PLL generates a pixel clock from HSYNCThe AD9888 is a comp ..
AD9888KSZ-170 , 100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface
ADSP-2115KS-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 1768-Pin PGA (ADSP-2101) . . . ..
ADSP-2115KS-80 ,ADSP-2100 Family DSP MicrocomputersSPECIFICATIONSPACKAGE OUTLINE DIMENSIONS(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . ..
ADSP-21160MKB-80 ,SHARC, 80 MHz, 600 MFLOPS, 3.3v I/O, 2.5v core, floating pointfeatures:ADSP-21160M is code compatible at the assembly level Two processing elements, each made ..
ADSP21160MKB-80 ,SHARC, 80 MHz, 600 MFLOPS, 3.3v I/O, 2.5v core, floating pointapplications. The ADSP-21160M Single-cycle Execution (with or without SIMD) of: A includes an 80 MH ..
ADSP-21161NCCA100 ,DSP MicrocomputerFEATURES (continued) 32-48, 16-48, 8-48 Execution Packing for Executing 1 M Bit On-Chip Dual-Ported ..
ADSP-21161NCCAZ100 , SHARC Processor
AD9887KS-100-AD9887KS-140
Dual Interface for Flat Panel Displays
REV.0
Dual Interface for
Flat Panel Displays
FEATURES
Analog Interface
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamp
4:2:2 Output Format Mode
Digital (DVI 1.0 Compatible) Interface
112 MHz Operation (1 Pixel/Clock Mode)
High Skew Tolerance of One Full Input Clock
Sync Detect for “Hot Plugging”
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Micro Displays
Digital TV
GENERAL DESCRIPTIONThe AD9887 offers designers the flexibility of a dual analog and
digital interface for flat panel displays (FPDs) on a single chip.
Both interfaces are optimized for excellent image quality supporting
display resolutions up to SXGA (1280 × 1024 at 75 Hz). Either the
analog or the digital interface can be selected by the user.
Analog InterfaceFor ease of design and to minimize cost, the AD9887 is a fully
integrated interface solution for FPDs. The AD9887 includes an
analog interface with a 140 MHz triple ADC with internal 1.25 V
reference, PLL to generate a pixel clock from HSYNC, program-
mable gain, offset, and clamp control. The user provides only a
3.3 V power supply, analog input, and HSYNC. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9887’s on-chip PLL generates a pixel clock from HSYNC.
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is 500 ps p-p typical at 140 MSPS. When a
COAST signal is presented, the PLL maintains its output fre-
quency in the absence of HSYNC. A sampling phase adjustment is
provided. Data, HSYNC and Clock output phase relationships are
maintained. The PLL can be disabled and an external clock input
provided as the pixel clock. The AD9887 also offers full sync pro-
cessing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. The analog interface
is fully programmable via a 2-wire serial interface.
FUNCTIONAL BLOCK DIAGRAM
Digital InterfaceThe AD9887 contains a Digital Video Interface (DVI 1.0) compat-
ible receiver. This receiver supports displays ranging from VGA
to SXGA (25 MHz to 112 MHz). The receiver operates with
true color (24-bit) panels in 1 or 2 pixel(s)/clock mode, and also
features an intrapair skew tolerance up to one full clock cycle.
Fabricated in an advanced CMOS process, the AD9887 is pro-
vided in a 160-lead MQFP surface mount plastic package and is
specified over the 0°C to 70°C temperature range.
AD9887–SPECIFICATIONS
ANALOG INTERFACEDIGITAL OUTPUTS
(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)
AD9887NOTESDrive Strength = 11.VCO Range = 01, Charge Pump Current = 001, PLL Divider = 1693.VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1600.DEMUX = 1, DATACK and DATACK Load = 10 pF, Data Load = 5 pF.Using external pixel clock.Simulated typical performance with package mounted to a 4-layer board.
Specifications subject to change without notice.
AD9887–SPECIFICATIONS
DIGITAL INTERFACEDC SPECIFICATIONS
(VD = 3.3 V, VDD = 3 V, Clock = Maximum)
AD9887NOTESThe typical pattern contains a gray scale area, Output Drive = High.The worst-case pattern contains a black and white checkerboard pattern, Output Drive = High.The setup and hold times with respect to the DATACK rising edge are the same as the falling edge.1 Pixel/clock mode, DATACK and DATACK Load = 10 pF, Data Load = 5 pF.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9887 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . .–25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS
ORDERING GUIDE
AD9887
PIN CONFIGURATION
RED B<0>RED B<1>RED B<2>RED B<3>RED B<4>RED B<5>RED B<6>RED B<7>GNDV
RED A<0>RED A<1>RED A<2>RED A<3>RED A<4>RED A<5>RED A<6>RED A<7>GNDV
SOGOUTHSOUTVSOUTDES
CDT
DATACKDATACKGNDV
GNDGNDSCAN
GNDV
REF
OUT
REF
GNDGND
GNDGND
GND
SCAN
OUT
CTL0CTL1CTL2CTL3
SCAN
CLK
GND
TERM
Rx2+Rx2
GND
Rx1+Rx1
GND
Rx0+Rx0
GND
RxC+RxC
GNDNCNC
GND
GND
FILT
GND
VDD
GND
GREEN A<7>
GREEN A<6>
GREEN A<5>
GREEN A<4>
GREEN A<3>
GREEN A<2>
GREEN A<1>
GREEN A<0>
VDD
GND
GREEN B<7>
GREEN B<6>
GREEN B<5>
GREEN B<4>
GREEN B<3>
GREEN B<2>
GREEN B<1>
GREEN B<0>
VDD
GND
BLUE A<7>
BLUE A<6>
BLUE A<5>
BLUE A<4>
BLUE A<3>
BLUE A<2>
BLUE A<1>
BLUE A<0>
VDD
GND
BLUE B<7>
BLUE B<6>
BLUE B<5>
BLUE B<4>
BLUE B<3>
BLUE B<2>
BLUE B<1>
BLUE B<0>
RMIDSCV
RAIN
RCLAMPV
GND
GND
GND
GMIDSCV
GAIN
GCLAMPV
SOGIN
GND
GND
GND
BMIDSCV
BAIN
BCLAMPV
GND
GND
CKINV
CLAMP
SDA
SCL
PVD
PVD
GND
GND
COAST
CKEXT
HSYNC
VSYNC
NC = NO CONNECT
Table I.Complete Pinout ListInputs
External
Sync/Clock
Inputs
Clamp Voltages
Scan Function
Data Inputs
Digital Video
AD9887
DESCRIPTIONS OF PINS SHARED BETWEEN ANALOG
AND DIGITAL INTERFACESHSOUTHorizontal Sync Output
A reconstructed and phase-aligned version of
the video HSYNC. The polarity of this output
can be controlled via a serial bus bit. In analog
interface mode the placement and duration
are variable. In digital interface mode the
placement and duration are set by the graphics
transmitter.
VSOUTVertical Sync Output
The separated VSYNC from a composite
signal or a direct pass through of the VSYNC
input. The polarity of this output can be con-
trolled via a serial bus bit. The placement and
duration in all modes is set by the graphics
transmitter.
Serial Port (2-Wire)SDASerial Port Data I/O
SCLSerial Port Data ClockSerial Port Address Input 1Serial Port Address Input 2
For a full description of the 2-wire serial regis-
ter and how it works, refer to the Control
Register section.
Data OutputsRED AData Output, Red Channel, Port A/Even
RED BData Output, Red Channel, Port B/Odd
GREEN AData Output, Green Channel, Port A/Even
GREEN BData Output, Green Channel, Port B/Odd
BLUE AData Output, Blue Channel, Port A/Even
BLUE BData Output, Blue Channel, Port B/Odd
The main data outputs. Bit 7 is the MSB.
These outputs are shared between the two
interfaces and behave according to which
interface is active. Refer to the sections on the
two interfaces for more information on how
these outputs behave.
Data Clock OutputsDATACKData Output Clock
DATACKData Output Clock Complement
Just like the data outputs, the data clock out-
puts are shared between the two interfaces.
They also behave differently depending on
which interface is active. Refer to the sections
on the two interfaces to determine how these
pins behave.
VariousSCDTChip Active/Inactive Detect Output
The logic for the SCDT pin is [analog interface
HSYNC detection] OR [digital interface DE
detection]. So, the SCDT pin will switch to
logic LOW under two conditions, when nei-
ther interface is active or when the chip is in
full chip power-down mode. The data outputs
are automatically three-stated when SCDT is
LOW. This pin can be read by a controller in
order to determine periods of inactivity.
SCAN FunctionSCANINData Input for SCAN Function
Data can be loaded serially into the 48-bit
SCAN register through this pin, clocking it in
with the SCANCLK pin. It then comes out of
the 48 data outputs in parallel. This function
is useful for loading known data into a graph-
ics controller chip for testing purposes.
SCANOUTData Output for SCAN Function
The data in the 48-bit SCAN register can be
read through this pin. Data is read on a FIFO
basis and is clocked via the SCANCLK pin.
SCANCLKData Clock for SCAN Function
This pin clocks the data through the SCAN
register. It controls both data input and data
output.
Table II.Analog Interface Pin ListClamp Voltages
PLL Filter
Power Supply
PIN FUNCTION DETAILS (ANALOG INTERFACE)
InputsRAINAnalog Input for RED Channel
GAINAnalog Input for GREEN Channel
BAINAnalog Input for BLUE Channel
High-impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. For RGB, the three channels are
identical and can be used for any colors, but
colors are assigned for convenient reference.
For proper 4:2:2 formatting in a YUV appli-
cation, the Y channel must be connected to
the GAIN input, U must be connected to the
BAIN input, and V must be connected to the
RAIN input.
They accommodate input signals ranging
from 0.5 V to 1.0 V full scale. Signals should
be ac-coupled to these pins to support clamp
operation.
HSYNCHorizontal Sync Input
This input receives a logic signal that estab-
lishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.
Polarity = 0, the falling edge of HSYNC is
used. When HSYNC Polarity = 1, the rising
edge is active.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.
Electrostatic Discharge (ESD) protection
diodes will conduct heavily if this pin is driven
more than 0.5 V above the maximum toler-
ance voltage (3.3 V), or more than 0.5 V
below ground.
VSYNCVertical Sync Input
This is the input for vertical sync.
SOGINSync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally
generated threshold, which is set to 0.15 V
above the negative peak of the input signal.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.
AD9887CLAMPExternal Clamp Input (Optional)
This logic input may be used to define the
time during which the input signal is clamped
to the reference dc level, (ground for RGB or
midscale for YUV). It should be exercised
when the reference dc level is known to be
present on the analog input channels, typically
during the back porch of the graphics signal.
The CLAMP pin is enabled by setting control
bit EXTCLMP to 1, (the default power-up is 0).
When disabled, this pin is ignored and the
clamp timing is determined internally by
counting a delay and duration from the trailing
edge of the HSYNC input. The logic sense of
this pin is controlled by CLAMPOL. When
not used, this pin must be grounded and
EXTCLMP programmed to 0.
COASTClock Generator Coast Input (Optional)
This input may be used to cause the pixel clock
generator to stop synchronizing with HSYNC
and continue producing a clock at its current
frequency and phase. This is useful when
processing signals from sources that fail to
produce horizontal sync pulses when in the
vertical interval. The COAST signal is generally
not required for PC-generated signals. Appli-
cations requiring COAST can do so through
the internal COAST found in the SYNC
processing engine.
The logic sense of this pin is controlled by
COAST Polarity.
When not used, this pin may be grounded and
COAST Polarity programmed to 1, or tied
HIGH and COAST Polarity programmed to 0.
COAST Polarity defaults to 1 at power-up.
CKEXTExternal Clock Input (Optional)
This pin may be used to provide an external
clock to the AD9887, in place of the clock
internally generated from HSYNC.
It is enabled by programming EXTCLK to 1.
When an external clock is used, all other internal
functions operate normally. When unused, this
pin should be tied to VDD or to GROUND, and
EXTCLK programmed to 0. The clock phase
adjustment still operates when an external clock
source is used.
CKINVSampling Clock Inversion (Optional)
This pin may be used to invert the pixel
sampling clock, which has the effect of
shifting the sampling phase 180°. This is in
support of Alternate Pixel Sampling mode,
wherein higher-frequency input signals (up
to 280 Mpps) may be captured by first sam-
pling the odd pixels, then capturing the even
This pin should be exercised only during blanking
intervals (typically vertical blanking) as it may
produce several samples of corrupted data during
the phase shift.
CKINV should be grounded when not used.
OutputsDRA7-0Data Output, Red Channel, Port A
DRB7-0Data Output, Red Channel, Port B
DGA7-0Data Output, Green Channel, Port A
DGB7-0Data Output, Green Channel, Port B
DBA7-0Data Output, Blue Channel, Port A
DBB7-0Data Output, Blue Channel, Port B
These are the main data outputs. Bit 7 is the MSB.
Each channel has two ports. When the part is
operated in single-channel mode (DEMUX = 0),
all data are presented to Port A, and Port B is
placed in a high-impedance state.
Programming DEMUX to 1 established dual-
channel mode, wherein alternate pixels are
presented to Port A and Port B of each chan-
nel. These will appear simultaneously, two
pixels presented at the time of every second
input pixel, when PAR is set to 1 (parallel
mode). When PAR = 0, pixel data appear
alternately on the two ports, one new sample
with each incoming pixel (interleaved mode).
In dual channel mode, the first pixel after
HSYNC is routed to Port A. The second pixel
goes to Port B, the third to A, etc.
The delay from pixel sampling time to output is
fixed. When the sampling time is changed by
adjusting the PHASE register, the output timing is
shifted as well. The DATACK, DATACK, and
HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
DATACKData Output Clock
DATACKData Output Clock Complement
Differential data clock output signals to be
used to strobe the output data and HSOUT
into external logic.
They are produced by the internal clock gen-
erator and are synchronous with the internal
pixel sampling clock.
When the AD9887 is operated in single-chan-
nel mode, the output frequency is equal to the
pixel sampling frequency. When operating in
dual channel mode, the clock frequency is one-
half the pixel frequency.
When the sampling time is changed by adjusting
the PHASE register, the output timing is shifted
as well. The Data, DATACK, DATACK, and
Either or both signals may be used, depend-
ing on the timing mode and interface design
employed.
HSOUTHorizontal Sync Output
A reconstructed and phase-aligned version of
the Hsync input. Both the polarity and dura-
tion of this output can be programmed via
serial bus registers.
By maintaining alignment with DATACK,
DATACK, and Data, data timing with
respect to horizontal sync can always be
determined.
SOGOUTSync-On-Green Slicer Output
This pin can be programmed to output
either the output from the Sync-On-Green
slicer comparator or an unprocessed but
delayed version of the HSYNC input. See
the Sync Block Diagram to view how this
pin is connected.
(Note: The output from this pin is the sliced
SOG, without additional processing from the
AD9887.)
Analog InterfaceREFOUTInternal Reference Output
Output from the internal 1.25 V bandgap refer-
ence. This output is intended to drive relatively
light loads. It can drive the AD9887 Reference
Input directly, but should be externally buff-
ered if it is used to drive other loads as well.
The absolute accuracy of this output is ±4%,
and the temperature coefficient is ±50 ppm,
which is adequate for most AD9887 appli-
cations. If higher accuracy is required, an
external reference may be employed instead.
If an external reference is used, connect this
pin to ground through a 0.1 µF capacitor.
REFINReference Input
The reference input accepts the master refer-
ence voltage for all AD9887 internal circuitry
(1.25 V ±10%). It may be driven directly by
the REFOUT pin. Its high impedance pre-
sents a very light load to the reference source.
This pin should always be bypassed to Ground
with a 0.1 µF capacitor.
FILTExternal Filter Connection
For proper operation, the pixel clock genera-
tor PLL requires an external filter. Connect
the filter shown Figure 7 to this pin. For
optimal performance, minimize noise and
parasitics on this node.
Power SupplyMain Power Supply
These pins supply power to the main elements
of the circuit. It should be filtered to be as
quiet as possible.
VDDDigital Output Power Supply
These supply pins are identified separately
from the VD pins so special care can be taken
to minimize output noise transferred into the
sensitive analog circuitry.
If the AD9887 is interfacing with lower-
voltage logic, VDD may be connected to a
lower supply voltage (as low as 2.2 V) for
compatibility.
PVDClock Generator Power Supply
The most sensitive portion of the AD9887 is
the clock generation circuitry. These pins
provide power to the clock PLL and help the
user design for optimal performance. The
designer should provide noise-free power to
these pins.
GNDGround
The ground return for all circuitry on chip.
It is recommended that the application circuit
board have a single, solid ground plane.
THEORY OF OPERATION (INTERFACE DETECTION)
Active Interface Detection and SelectionThe AD9887 includes circuitry to detect whether or not an
interface is active.
For detecting the analog interface, the circuitry monitors the
presence of HSYNC, VSYNC, and Sync-on-Green. The result of
the detection circuitry can be read from the 2-wire serial inter-
face bus at address 11H Bits 7, 6, and 5 respectively. If one of
these sync signals disappears, the maximum time it takes for the
circuitry to detect it is 100 ms.
There are two stages for detecting the digital interface. The first
stage searches for the presence of the digital interface clock.
The circuitry for detecting the digital interface clock is active
even when the digital interface is powered down. The result of
this detection stage can be read from the 2-wire serial interface
bus at address 11H Bit 4. If the clock disappears, the maximum
time it takes for the circuitry to detect it is 100 ms. The second
stage attempts to detect DE on the digital interface. Detection is
accomplished when 32 DEs have been counted. DE can only be
detected when the digital interface is powered up, so it is not
always active. The DE detection circuitry is one of the logic
inputs used to set the SyncDT output pin (Pin 136). The logic
for the SyncDT pin is [DE detect] OR [HSYNC detect].
There is an override for the automatic interface selection. It is
the AIO bit (Active Interface Override). When the AIO bit is set
to Logic 0, the automatic circuitry will be used. When the AIO
bit is set to Logic 1, the AIS bit will be used to determine the
active interface rather than the automatic circuitry.
AD9887
Table III.Interface Selection Controls
Table IV.Power-Down Mode DescriptionsSoft Power-Down (Seek Mode)
Digital Interface On
Analog Interface On
NOTESPower-down is controlled via bit 0 in serial bus Register 12h.Analog Interface Detect is determined by OR-ing Bits 7, 6, and 5 in serial bus Register 11h.Digital Interface Detect is determined by Bit 4 in serial bus Register 11h.
Power ManagementThe AD9887 is a dual interface device with shared outputs.
Only one interface can be used at a time. For this reason, the
chip automatically powers down the unused interface. When
the analog interface is being used, most of the digital interface
circuitry is powered down and vice-versa. This helps to minimize
the AD9887 total power dissipation. In addition, if neither inter-
face has activity on it, the chip powers down both interfaces.
The AD9887 uses the activity detect circuits, the active inter-
face bits in the serial registers, the active interface override bits,
and the power-down bit to determine the correct power state.
In a given power mode not all circuitry in the inactive interface
is powered down completely. When the digital interface is
active, the bandgap reference and HSYNC detect circuitry is not
powered down. When the analog interface is active, the digital
interface clock detect circuit is not powered down. Table IV
summarizes how the AD9887 determines which power mode to
be in and what circuitry is powered on/off in each of these
modes. The power-down command has priority, followed by the
active interface override, and then the automatic circuitry.
THEORY OF OPERATION AND DESIGN GUIDE
(ANALOG INTERFACE)
General DescriptionThe AD9887 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The device is ideal for implementing a computer
interface in HDTV monitors or as the front end to high-
performance video scan converters.
Implemented in a high-performance CMOS process, the inter-
face can capture signals with pixel rates of up to 140 MHz and,
with an Alternate Pixel Sampling mode, up to 280 MHz.
The AD9887 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control,
and output data formatting. All controls are programmable via
a 2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensi-
tive to the physical and electrical environment.
With a typical power dissipation of less than 725 mW and an
operating temperature range of 0°C to 70°C, the device requires
no special environmental considerations.
Input Signal HandlingThe AD9887 has three high-impedance analog input pins for
the Red, Green, and Blue channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-lead D connector, or BNC connectors.
The AD9887 should be located as close as practical to the
input connector. Signals should be routed via matched-impedance
traces (normally 75 Ω) to the IC input pins.
At that point the signal should be resistively terminated (75 Ω
to the signal ground return) and capacitively coupled to the
AD9887 inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best per-
formance can be obtained with the widest possible signal bandwidth.
The wide bandwidth inputs of the AD9887 (330 MHz) can
track the input signal continuously as it moves from one pixel
level to the next, and digitize the pixel during a long, flat pixel
time. In many systems, however, there are mismatches, reflec-
tions, and noise, which can result in excessive ringing and
distortion of the input waveform. This makes it more difficult
to establish a sampling phase that provides good image quality.
It has been shown that a small inductor in series with the input
is effective in rolling off the input bandwidth slightly, and pro-
viding a high quality signal over a wider range of conditions.
Using a Fair-Rite #2508051217Z0 High-Speed Signal Chip
Bead inductor in the circuit of Figure 1 gives good results in
most applications.
HSYNC, VSYNC InputsThe AD9887 receives a horizontal sync signal and uses it to
generate the pixel clock and clamp timing. It is possible to operate
the AD9887 without applying HSYNC (using an external clock,
external clamp) but a number of features of the chip will be
unavailable, so it is recommended that HSYNC be provided.
This can be either a sync signal directly from the graphics
source, or a preprocessed TTL or CMOS level signal.
The HSYNC input includes a Schmitt trigger buffer and is capable
of handling signals with long rise times, with superior noise
immunity. In typical PC-based graphic systems, the sync signals
are simply TTL-level drivers feeding unshielded wires in the
monitor cable. As such, no termination is required or desired.
When the VSYNC input is selected as the source for VSYNC, it is
used for COAST generation and is passed through to the
VSOUT pin.
Serial Control PortThe serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150 Ω series resistors placed between the pull-up resistors and
the input pins.
Output Signal HandlingThe digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB ClampingTo digitize the incoming signal properly, the dc offset of the
input must be adjusted to fit the range of the on-board A/D
converters.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. The white level will then be
approximately 1.0 V. Some common RGB line amplifier boxes
use emitter-follower buffers to split signals and increase drive
capability. This introduces a 700 mV dc offset to the signal, which
is removed by clamping for proper capture by the AD9887.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. Originating
from CRT displays, the electron beam is “blanked” by sending a
black level during horizontal retrace to prevent disturbing the
image. Most graphics systems maintain this format of sending a
black level between active video lines.
An offset is then introduced which results in the A/D converters
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In systems with embedded sync, a blacker-than-black signal
(HSYNC) is produced briefly to signal the CRT that it is time
to begin a retrace. For obvious reasons, it is important to avoid
AD9887clamping on the tip of HSYNC. Fortunately, there is virtually
always a period following HSYNC called the back porch where
a good black reference is provided. This is the time when clamp-
ing should be done.
The clamp timing can be established by exercising the CLAMP
pin at the appropriate time (with EXTCLMP = 1). The polarity
of this signal is set by the Clamp Polarity bit.
An easier method of clamp timing employs the AD9887 internal
clamp timing generator. The Clamp Placement register is pro-
grammed with the number of pixel clocks that should pass after
the trailing edge of HSYNC before clamping starts. A second
register (Clamp Duration) sets the duration of the clamp.
These are both 8-bit values, providing considerable flexibility in
clamp generation. The clamp timing is referenced to the trailing
edge of HSYNC, the back porch (black reference) always follows
HSYNC. A good starting point for establishing clamping is to
set the clamp placement to 08h (providing eight pixel periods
for the graphics signal to stabilize after sync) and set the clamp
duration to 14h (giving the clamp 20 pixel periods to reestablish
the black reference).
The value of the external input coupling capacitor affects the per-
formance of the clamp. If the value is too small, there can be an
amplitude change during a horizontal line time (between clamping
intervals). If the capacitor is too large, it will take excessively long for
the clamp to recover from a large change in incoming signal offset.
The recommended value (47 nF) results in recovery from a step error
of 100 mV to within 1/2 LSB in 10 lines using a clamp duration of
20 pixel periods on a 60 Hz SXGA signal.
YUV ClampingYUV signals are slightly different from RGB signals in that the
dc reference level (black level in RGB signals) will be at the
midpoint of the U and V video signal. For these signals it can
be necessary to clamp to the midscale range of the A/D con-
verter range (80h) rather than bottom of the A/D converter
range (00h).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 0Fh and are Bits 0–2.
The midscale reference voltage that each A/D converter clamps
to is provided independently on the RMIDSCV, GMIDSCV, and
BMIDSCV pins. Each converter must have its own midscale refer-
ence because both offset adjustment and gain adjustment for
each converter will affect the dc level of midscale.
During clamping, the Y and V converters are clamped to their
respective midscale reference input. These inputs are pins
BCLAMPV, and RCLAMPV for the U and V converters respectively.
The typical connections for both RGB and YUV clamping are
shown below in Figure 2. Note: if midscale clamping is not
required, all of the midscale voltage outputs should still be con-
nected to ground through a 0.1 µF capacitor.
Figure 2.Typical Clamp Configuration for RBG/YUV
Applications
Gain and Offset ControlThe AD9887 can accommodate input signals with inputs rang-
ing from 0.5 V to 1.0 V full scale. The full-scale range is set in
three 8-bit registers (Red Gain, Green Gain, and Blue Gain).
A code of 0 establishes a minimum input range of 0.5 V; 255
corresponds with the maximum range of 1.0 V. Note that
increasing the gain setting results in an image with less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset) provide independent settings for
each channel.
The offset controls provide a ±63 LSB adjustment range. This
range is connected with the full-scale range, so if the input range
is doubled (from 0.5 V to 1.0 V) then the offset step size is also
doubled (from 2 mV per step to 4 mV per step).
Figure 3 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero-scale level.
GAIN
00hFFh
INPUT RANGE
0.5Figure 3.Gain and Offset Control
Sync-on-GreenThe Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level from the incoming video signal with a
negative peak detector. Second, it sets the Sync trigger level
(nominally 150 mV above the negative peak). The exact trigger
level is variable and can be programmed via register 11H. The
Sync-on-Green input must be ac-coupled to the green analog
input through its own capacitor as shown in Figure 4. The value
of the capacitor must be 1 nF ±20%. If Sync-on-Green is not
used, this connection is not required and SOGIN should be left
unconnected. (Note: The Sync-on-Green signal is always nega-
tive polarity.) Please refer to the Sync Processing section for more
information.
Figure 4.Typical Clamp Configuration for RGB/YUV
Applications
Clock GenerationA Phase Locked Loop (PLL) is employed to generate the pixel
clock. The HSYNC input provides a reference frequency for the
PLL. A Voltage Controlled Oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the
PLL divide value (Registers 01H and 02H) and phase compared
with the Hsync input. Any error is used to shift the VCO fre-
quency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period when the signal is slewing from the old pixel
amplitude and settling at its new value. Then there is a time
when the input voltage is stable, before the signal must slew to a
new value (see Figure 5). The ratio of the slewing time to the
stable time is a function of the bandwidth of the graphics DAC
and the bandwidth of the transmission system (cable and termi-
nation). It is also a function of the overall pixel rate. Clearly, if the
dynamic characteristics of the system remain fixed, the slewing
and settling times are likewise fixed. This time must be sub-
tracted from the total pixel period, leaving the stable period. At
higher pixel frequencies, the total cycle time is shorter, and the
stable pixel time becomes shorter as well.
Figure 5.Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9887’s
clock generation circuit to minimize jitter. As indicated in Fig-
ure 6, the clock jitter of the AD9887 is less than 6% of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.
The PLL characteristics are determined by the loop filter
design, by the PLL charge pump current and by the VCO range
setting. The loop filter design is illustrated in Figure 7. Recom-
mended settings of VCO range and charge pump current for
VESA standard display modes are listed in Table VII.
Figure 7.PLL Loop Filter Detail
Four programmable registers are provided to optimize the per-
formance of the PLL. These registers are:The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock fre-
quencies in the range of 12 MHz to 140 MHz. The Divisor
Register controls the exact multiplication factor. This register
may be set to any value between 221 and 4095. (The divide
ratio that is actually used is the programmed divide ratio
plus one.)The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO Range register sets this operating range.
Because there are only four possible regions, only the two
least-significant bits of the VCO Range register are used.
The frequency ranges for the lowest and highest regions
are shown in Table V.
AD9887
Table V.VCO Frequency Ranges
Table VI.Charge Pump Current/Control BitsThe 3-Bit Charge Pump Current Register. This register
allows the current that drives the low pass loop filter to be
varied. The possible current values are listed in Table VI.
provides 32 phase-shift steps of 11.25° each. The Hsync
signal with an identical phase shift is available through the
HSOUT pin. Phase adjustment is still available if the pixel
clock is being provided externally.The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sam-
pling point within a clock cycle. The Phase Adjust register
The COAST allows the PLL to continue to run at the same
frequency, in the absence of the incoming Hsync signal. This
may be used during the vertical sync period, or any other
time that the Hsync signal is unavailable. The polarity of
the COAST signal may be set through the Coast Polarity Bit.
Also, the polarity of the Hsync signal may be set through the
HSYNC polarity Bit. If not using automatic polarity
detection, the HSYNC and COAST polarity bits should
be set to match the Polarity of their respective signals.
Table VII.Recommended VCO Range and Charge Pump Current Settings for Standard Display FormatsSVGA
XGA
SXGA
UXGA
*Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.
Figure 8.ADC Block Diagram (Single Channel Output)
Figure 9.Relationship of Offset Range to Input Range
SCAN FunctionThe SCAN function is intended as a pseudo JTAG function for
manufacturing test of the board. The ordinary operation of the
AD9887 is disabled during SCAN.
To enable the SCAN function, set register 14h, bit 2 to 1. To
SCAN in data to all 48 digital outputs, apply 48 serial bits of
data and 48 clocks (typically 5MHz, max of 20MHz) to the
SCANIN and SCANCLK pins respectively. The data is shifted
in on the rising edge of SCANCLK. The first serial bit shifted
in will appear at the RED A<7> output after one clock cycle.
After 48 clocks, the first bit is shifted all the way to the BLU
B<0>. The 48th bit will now be at the RED A<7> output. If
SCANCLK continues after 48 cycles, the data will continue to be
shifted from RED A<7> to BLU B<0> and will come out of the
SCANOUT pin as serial data on the falling edge of SCANCLK.
This is illustrated in Figure 10. A setup time (tSU) of 3ns
should be plenty and no hold time (tHOLD) is required (≥ 0ns).
This is illustrated in Figure 11.
Figure 11.SCAN Setup and Hold
Alternate Pixel Sampling ModeA Logic 1 input on Clock Invert (CKINV, Pin 94) inverts the
nominal ADC clock. CKINV can be switched between frames
to implement the alternate pixel sampling mode. This allows
higher effective image resolution to be achieved at lower pixel
rates but with lower frame rates.
On one frame, only even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire
frame in the graphics controller, a complete image can be recon-
structed. This is very similar to the interlacing process that is
employed in broadcast television systems, but the interlacing is
vertical instead of horizontal. The frame data is still presented to
the display at the full desired refresh rate (usually 60 Hz) so no
flicker artifacts are added.
Figure 12.Odd and Even Pixels in a Frame
Figure 13.Odd Pixels from Frame 1
AD9887Figure 14.Even Pixels from Frame 2
Figure 15.Combine Frame Output from Graphics Controller
Figure 16.Subsequent Frame from Controller
Timing (Analog Interface)The following timing diagrams show the operation of the
AD9887 analog interface in all clock modes. The part estab-
lishes timing by having the sample that corresponds to the pixel
digitized when the leading edge of HSYNC occurs sent to the
“A” data port. In Dual Channel Mode, the next sample is sent
to the “B” port. Future samples are alternated between the “A”
and “B” data ports. In Single Channel Mode, data is only sent
to the “A” data port, and the “B” port is placed in a high
impedance state.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally.
Figure 17.Analog Output Timing
Hsync TimingHorizontal sync is processed in the AD9887 to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems use
Hsync to align memory and display write cycles, so it is important
to have a stable timing relationship between Hsync output
(HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9887. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (Register 04H, Bit 4).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via Regis-
ter 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
Coast TimingIn most computer systems, the Hsync signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
In some systems, however, Hsync is disturbed during the Verti-
cal Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embed Sync-On-Green (SOG), Hsync includes
equalization pulses or other distortions during Vsync. To avoid
upsetting the clock generator during Vsync, it is important to
ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it will attempt to lock to this new frequency, and will
have changed frequency by the end of the Vsync period. It will
then take a few lines of correct Hsync timing to recover at the
beginning of a new frame, resulting in a “tearing” of the image
at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
Coast can be provided by the graphics controller or it can be
internally generated by the AD9887 Sync processing engine.
Figure 18.Single Channel Mode (Analog Interface)
Figure 19.Single Channel Mode, 2 Pixels/Clock (Even Pixels) (Analog Interface)
Figure 20.Single Channel Mode, 2 Pixels/Clock (Odd Pixels) (Analog Interface)
AD9887Figure 21.Dual Channel Mode, Interleaved Outputs (Analog Interface), Outphase = 1
Figure 22.Dual Channel Mode, Parallel Outputs (Analog Interface), Outphase = 1
