AD9883KST-110 ,110 MSPS Analog Interface for Flat Panel DisplaysSPECIFICATIONSAnalog Interface (V = 3.3 V, V = 3.3 V, ADC Clock = Maximum Conversion Rate)D DDTest ..
AD9884 ,Triple 8-Bit, 140 MSPS ADC, RGB Graphics Digitizer for SXGA LCD MonitorsSPECIFICATIONSTest AD9884AKS-100 AD9884AKS-140Parameter Temp Level Min Typ Max Min Typ Max UnitRESO ..
AD9884A ,100 MSPS/140 MSPS Analog Flat Panel InterfaceCHARACTERISTICSq –Junction-to-CaseJCThermal Resistance V 8.4 8.4
AD9883KST-110
110 MSPS Analog Interface for Flat Panel Displays
REV.0
110 MSPS Analog Interface for
Flat Panel Displays
FUNCTIONAL BLOCK DIAGRAM
FEATURES
110 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for ”Hot Plugging”
Midscale Clamping
Power-Down Mode
Low Power:500 mW Typical
Composite Sync Applications Require an External Coast
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
GENERAL DESCRIPTIONThe AD9883 is a complete 8-bit, 110 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 110 MSPS encode
rate capability and full-power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280 × 1024 at 60 Hz).
The AD9883 includes a 110 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and HSYNC and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9883’s on-chip PLL generates a pixel clock from HSYNC
and COAST inputs. Pixel clock output frequencies range from
12 MHz to 110 MHz. PLL clock jitter is 500 ps p-p typical at
110 MSPS. When the COAST signal is presented, the PLL
maintains its output frequency in the absence of HSYNC. A
sampling phase adjustment is provided. Data, HSYNC and
Clock output phase relationships are maintained. The AD9883
also offers full sync processing for composite sync and sync-on-
green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully pro-
grammable via a two-wire serial interface.
Fabricated in an advanced CMOS process, the AD9883 is
provided in a space-saving 80-lead LQFP surface mount plastic
package and is specified over the 0°C to 70°C temperature range.
AD9883–SPECIFICATIONS
(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate)Analog Interface DIGITAL INPUTS
AD9883NOTESVCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.DATACK Load = 15 pF, Data Load = 5 pF.
Specifications subject to change without notice.
AD9883
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9883 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . .–25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.100% production tested at 25°C and sample tested at
specified temperatures.
IIISample tested only.Parameter is guaranteed by design and characterization testing.Parameter is a typical value only.100% production tested at 25°C; guaranteed by design and
characterization testing.
ORDERING GUIDE
Table I.Complete Pinout List
PIN CONFIGURATION
GND
GREEN <7>
GREEN <6>
GREEN <5>
GREEN <4>
GREEN <3>
GREEN <2>
GREEN <1>
GREEN <0>
GND
VDD
BLUE <7>
BLUE <6>
BLUE <5>
BLUE <4>
BLUE <3>
BLUE <2>
BLUE <1>
BLUE <0>
GND
GND
GND
GND
GND
GND
GND
REF BYPASS
SDA
SCL
RAIN
GAIN
BAIN
SOGIN
NC = NO CONNECT
GNDVDDVDDRED <0>RED <1>RED <2>RED <3>RED <4>RED <5>RED <6>RED <7>VDDGNDDATACKHSOUTSOGOUTGNDVDGNDVSOUT
GND
VDDVDD
GNDGND
PVD
GND
MIDSCV
CLAMP
GND
COASTHSYNCVSYNC
GND
FILTPVD
GND
AD9883
PIN FUNCTION DETAIL
OutputsHSOUTHorizontal Sync Output
A reconstructed and phase-aligned version of
the Hsync input. Both the polarity and dura-
tion of this output can be programmed via
serial bus registers.
By maintaining alignment with DATACK,
and Data, data timing with respect to horizon-
tal sync can always be determined.
VSOUTVertical Sync Output
A reconstructed and phase-aligned version of
the video Vsync. The polarity of this output
can be controlled via a serial bus bit. The place-
ment and duration in all modes is set by the
graphics transmitter.
SOGOUTSync On Green Slicer Output
This pin outputs either the signal from the
Sync-On-Green slicer comparator or an unproc-
essed but delayed version of the Hsync input.
See the Sync Block Diagram (Figure 11) to
view how this pin is connected.
(Note: Besides slicing off SOG, the output from
this pin gets no other additional processing on
the AD9883. Vsync separation is performed via
the sync separator.)
Serial Port
(Two-Wire)SDASerial Port Data I/O
SCLSerial Port Data ClockSerial Port Address Input 1
For a full description of the two-wire serial
register and how it works, refer to the Two-
Wire Serial Control Port section.
Data OutputsREDData Output, Red Channel
GREENData Output, Green Channel
BLUEData Output, Blue Channel
The main data outputs. Bit 7 is the MSB. The
delay from pixel sampling time to output is
fixed. When the sampling time is changed by
adjusting the PHASE register, the output timing
is shifted as well. The DATACK and HSOUT
outputs are also moved, so the timing rela-
tionship among the signals is maintained. For
exact timing information, refer to Figures 7
and 8.
Data Clock
OutputDATACKData Output Clock
This is the main clock output signal used to
strobe the output data and HSOUT into
external logic.
When the sampling time is changed by adjust-
ing the PHASE register, the output timing is
shifted as well. The Data, DATACK, and
HSOUT outputs are all moved, so the timing
relationship among the signals is maintained.
InputsRAINAnalog Input for RED Channel
GAINAnalog Input for GREEN Channel
BAINAnalog Input for BLUE Channel
High-impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. (The three channels are identical,
and can be used for any colors, but colors are
assigned for convenient reference.)
They accommodate input signals ranging from
0.5 V to 1.0 V full scale. Signals should be
ac-coupled to these pins to support clamp
operation.
HSYNCHorizontal Sync Input
This input receives a logic signal that estab-
lishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.
The logic sense of this pin is controlled by
serial register 0Eh Bit 6 (Hsync Polarity). Only
the leading edge of Hsync is active, the trailing
edge is ignored. When Hsync Polarity = 0, the
falling edge of Hsync is used. When Hsync
Polarity = 1, the rising edge is active.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.
VSYNCVertical Sync Input
This is the input for vertical sync.
SOGINSync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally gener-
ated threshold. The threshold level can be
programmed in 10 mV steps to any voltage
between 10 mV and 330 mV above the negative
peak of the input signal. The default voltage
threshold is 150 mV.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce
a noninverting digital output on SOGOUT.
(This is usually a composite sync signal, contain-
ing both vertical and horizontal sync information
that must be separated before passing the hori-
zontal sync signal to Hsync.)
When not used, this input should be left uncon-
nected. For more details on this function and
CLAMPExternal Clamp Input
This logic input may be used to define the
time during which the input signal is clamped
to ground. It should be exercised when the
reference dc level is known to be present on
the analog input channels, typically during the
back porch of the graphics signal. The CLAMP
pin is enabled by setting control bit Clamp
Function to 1, (register 0FH, Bit 7, default is
0). When disabled, this pin is ignored and the
clamp timing is determined internally by count-
ing a delay and duration from the trailing edge
of the HSYNC input. The logic sense of this pin
is controlled by Clamp Polarity register 0FH,
Bit 6. When not used, this pin must be grounded
and Clamp Function programmed to 0.
COASTClock Generator Coast Input (Optional)
This input may be used to cause the pixel
clock generator to stop synchronizing with
Hsync and continue producing a clock at its
current frequency and phase. This is useful
when processing signals from sources that fail
to produce horizontal sync pulses during the
vertical interval. The COAST signal is gener-
ally NOT required for PC-generated signals.
The logic sense of this pin is controlled by
Coast Polarity, (register 0FH, Bit 3).
When not used, this pin may be grounded
and Coast Polarity programmed to 1, or tied
HIGH (to VD through a 10 kΩ resistor) and
Coast Polarity programmed to 0. Coast
Polarity defaults to 1 at power-up.
REF BYPASSInternal Reference BYPASS
Bypass for the internal 1.25 V bandgap ref-
erence. It should be connected to ground
through a 0.1 µF capacitor.
The absolute accuracy of this reference is ±4%,
and the temperature coefficient is ±50 ppm,
which is adequate for most AD9883 applica-
tions. If higher accuracy is required, an external
reference may be employed instead.
MIDSCVMidscale Voltage Reference BYPASS
Bypass for the internal midscale voltage refer-
ence. It should be connected to ground through
a 0.1 µF capacitor. The exact voltage varies
with the gain setting of the BLUE channel.
FILTExternal Filter Connection
For proper operation, the pixel clock generator
PLL requires an external filter. Connect the
filter shown in Figure 6 to this pin. For optimal
performance, minimize noise and parasitics on
this node.
Power SupplyVDDDigital Output Power Supply
A large number of output pins (up to 25)
switching at high speed (up to 110 MHz)
generates a lot of power supply transients
(noise). These supply pins are identified sepa-
rately from the VD pins so special care can be
taken to minimize output noise transferred
into the sensitive analog circuitry.
If the AD9883 is interfacing with lower-voltage
logic, VDD may be connected to a lower supply
voltage (as low as 2.5 V) for compatibility.
PVDClock Generator Power Supply
The most sensitive portion of the AD9883 is
the clock generation circuitry. These pins
provide power to the clock PLL and help the
user design for optimal performance. The
designer should provide “quiet,” noise-free
power to these pins.
GNDGround
The ground return for all circuitry on chip. It
is recommended that the AD9883 be assembled
on a single solid ground plane, with careful
attention to ground current paths.
DESIGN GUIDE
General DescriptionThe AD9883 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel moni-
tors or projectors. The circuit is ideal for providing a computer
interface for HDTV monitors or as the front-end to high-
performance video scan converters.
Implemented in a high-performance CMOS process, the inter-
face can capture signals with pixel rates of up to 110 MHz.
The AD9883 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensitive
to the physical and electrical environment.
With a typical power dissipation of only 500 mW and an operat-
ing temperature range of 0°C to 70°C, the device requires no
special environmental considerations.
Digital InputsAll digital inputs on the AD9883 operate to 3.3 V CMOS levels.
However, all digital inputs are 5 V tolerant. (Applying 5 V to
them will not cause any damage.)
Input Signal HandlingThe AD9883 has three high-impedance analog input pins for
the Red, Green, and Blue channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or via BNC connectors.
AD9883At that point the signal should be resistively terminated (75 Ω to
the signal ground return) and capacitively coupled to the AD9883
inputs through 47 nF capacitors. These capacitors form part of
the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best perfor-
mance can be obtained with the widest possible signal bandwidth.
The ultrawide bandwidth inputs of the AD9883 (300 MHz) can
track the input signal continuously as it moves from one pixel level
to the next, and digitize the pixel during a long, flat pixel time. In
many systems, however, there are mismatches, reflections, and
noise, which can result in excessive ringing and distortion of the
input waveform. This makes it more difficult to establish a sam-
pling phase that provides good image quality. It has been shown
that a small inductor in series with the input is effective in
rolling off the input bandwidth slightly, and providing a high
quality signal over a wider range of conditions. Using a Fair-
Rite #2508051217Z0- High-Speed Signal Chip Bead inductor
in the circuit of Figure 1 gives good results in most applications.
Figure 1.Analog Input Interface Circuit
Hsync, Vsync InputsThe interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. This can be either
a sync signal directly from the graphics source, or a preprocessed
TTL or CMOS level signal.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no ter-
mination is required.
Serial Control PortThe serial control port is designed for 3.3 V logic. If there are 5 V
drivers on the bus, these pins should be protected with 150 Ω series
resistors placed between the pull-up resistors and the input pins.
Output Signal HandlingThe digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB ClampingTo properly digitize the incoming signal, the dc offset of the input
must be adjusted to fit the range of the on-board A/D converters.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately
1.0 V. Some common RGB line amplifier boxes use emitter-
follower buffers to split signals and increase drive capability.
This introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9883.
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to elimi-
nate offset errors.
In most pc graphics systems, black is transmitted between active
video lines. With CRT displays, when the electron beam has
completed writing a horizontal line on the screen (at the right
side), the beam is deflected quickly to the left side of the screen
(called horizontal retrace) and a black signal is provided to
prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually
always a period following Hsync called the back porch where a
good black reference is provided. This is the time when clamp-
ing should be done.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with External Clamp = 1).
The polarity of this signal is set by the Clamp Polarity bit.
A simpler method of clamp timing employs the AD9883 internal
clamp timing generator. The Clamp Placement register is pro-
grammed with the number of pixel times that should pass after
the trailing edge of HSYNC before clamping starts. A second
register (Clamp Duration) sets the duration of the clamp.
These are both 8-bit values, providing considerable flexibility in
clamp generation. The clamp timing is referenced to the trailing
edge of Hsync because, though Hsync duration can vary widely,
the back porch (black reference) always follows Hsync. A good
starting point for establishing clamping is to set the clamp place-
ment to 09h (providing 9 pixel periods for the graphics signal to
stabilize after sync) and set the clamp duration to 14h (giving
the clamp 20 pixel periods to reestablish the black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capaci-
tor affects the performance of the clamp. If it is too small, there
will be a significant amplitude change during a horizontal line
time (between clamping intervals). If the capacitor is too large,
then it will take excessively long for the clamp to recover from a
large change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1/2 LSB in 10 lines with a clamp duration of 20 pixel
periods on a 60 Hz SXGA signal.
YUV ClampingYUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the graphics signal rather than the bottom. For
these signals it can be necessary to clamp to the midscale range
of the A/D converter range (80h) rather than bottom of the A/D
converter range (00h).
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in register 10h and are Bits 0–2. The midscale refer-
Figure 2.Gain and Offset Control
Gain and Offset ControlThe AD9883 can accommodate input signals with inputs rang-
ing from 0.5 V to 1.0 V full scale. The full-scale range is set in
three 8-bit registers (Red Gain, Green Gain, and Blue Gain).
Note that increasing the gain setting results in an image with less
contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset) provide independent settings for
each channel.
The offset controls provide a ±63 LSB adjustment range. This
range is connected with the full scale range, so if the input range
is doubled (from 0.5 V to 1.0 V) then the offset step size is also
doubled (from 2 mV per step to 4 mV per step).
Figure 2 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting in
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero scale level.
Sync-on-GreenThe Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level to a
programmable level (typically 150 mV) above the negative peak.
The Sync-on-Green input must be ac-coupled to the green
analog input through its own capacitor as shown below in
Figure 3. The value of the capacitor must be 1 nF ± 20%. If
Sync-on-Green is not used, this connection is not required.
(Note: The Sync on Green signal is always negative polarity.)
Clock GenerationA Phase Locked Loop (PLL) is employed to generate the pixel
clock. In this PLL, the Hsync input provides a reference fre-
quency. A Voltage Controlled Oscillator (VCO) generates a
much higher pixel clock frequency. This pixel clock is divided
by the PLL divide value (registers 01H and 02H) and phase
compared with the Hsync input. Any error is used to shift the
VCO frequency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (Figure 4). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable
and termination). It is also a function of the overall pixel rate.
Clearly, if the dynamic characteristics of the system remain
fixed, then the slewing and settling time is likewise fixed. This
time must be subtracted from the total pixel period, leaving the
stable period. At higher pixel frequencies, the total cycle time is
shorter, and the stable pixel time becomes shorter as well.
Figure 4.Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9883’s
clock generation circuit to minimize jitter. As indicated in Fig-
ure 5, the clock jitter of the AD9883 is less than 5% of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.
AD9883The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sampling
point within a clock cycle. The Phase Adjust register provides
32 phase-shift steps of 11.25° each. The Hsync signal with
an identical phase shift is available through the HSOUT pin.
The COAST pin is used to allow the PLL to continue to
run at the same frequency, in the absence of the incoming
HSYNC signal or during disturbances in Hsync (such as
equalization pulses). This may be used during the vertical
sync period, or any other time that the HSYNC signal is
unavailable. The polarity of the COAST signal may be set
through the Coast Polarity Register. Also, the polarity of the
HSYNC signal may be set through the HSYNC Polarity
Register. For both HSYNC and COAST, a value of “1” is
active high.
Power ManagementThe AD9883 uses the activity detect circuits, the active inter-
face bits in the serial bus, the active interface override bits, and
the power-down bit to determine the correct power state. There
are three power states, full-power, seek mode, and power-down.
Table IV summarizes how the AD9883 determines what power
mode to be in and what circuitry is powered on/off in each of
these modes. The power-down command has priority and then
the automatic circuitry.
Table IV. Power-Down Mode DescriptionsNOTESPower-Down is controlled via Bit 1 in serial bus register 0Fh.Sync Detect is determined by OR-ing Bits 7, 4, and 1 in serial bus register 14h.
The PLL characteristics are determined by the loop filter design,
by the PLL Charge Pump Current and by the VCO range setting.
The loop filter design is illustrated in Figure 6. Recommended
settings of VCO range and charge pump current for VESA
standard display modes are listed in Table V.
Figure 6.PLL Loop Filter Detail
Four programmable registers are provided to optimize the per-
formance of the PLL. These registers are:The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock fre-
quencies in the range of 12 MHz to 110 MHz. The Divisor
Register controls the exact multiplication factor. This regis-
ter may be set to any value between 221 and 4095. (The
divide ratio that is actually used is the programmed divide
ratio plus one.)The 2-Bit VCO Range Register. To improve the noise per-
formance of the AD9883, the VCO operating frequency
range is divided into three overlapping regions. The VCO
Range Register sets this operating range. The frequency ranges
for the lowest and highest regions are shown in Table II.
Table II.VCO Frequency RangesThe 3-Bit Charge Pump Current register. This register
allows the current that drives the low pass loop filter to be
varied. The possible current values are listed in Table III.
Table III.Charge Pump Current/Control BitsTimingThe following timing diagrams show the operation of the AD9883.
The Output Data Clock signal is created so that its rising edge
always occurs between data transitions, and can be used to latch
the output data externally.
There is a pipeline in the AD9883, which must be flushed before
valid data becomes available. This means four data sets are
presented before valid data is available.
Figure 7.Output Timing
Table V.Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Hsync TimingHorizontal Sync (Hsync) is processed in the AD9883 to elimi-
nate ambiguity in the timing of the leading edge with respect to
the phase-delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems
use Hsync to align memory and display write cycles, so it is
important to have a stable timing relationship between Hsync
output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9883. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be pro-
grammed either active high or active low (register 0EH, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via regis-
ter 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
AD9883
Coast TimingIn most computer systems, the Hsync signal is provided con-
tinuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used and
the pin should be permanently connected to the inactive state.
In some systems, however, Hsync is disturbed during the
Vertical Sync period (Vsync). In some cases, Hsync pulses
disappear. In other systems, such as those that employ Compos-
ite Sync (Csync) signals or embedded Sync-On-Green (SOG),
Hsync includes equalization pulses or other distortions during
Vsync. To avoid upsetting the clock generator during Vsync,
it is important to ignore these distortions. If the pixel clock
PLL sees extraneous pulses, it will attempt to lock to this new
frequency, and will have changed frequency by the end of the
Vsync period. It will then take a few lines of correct Hsync tim-
ing to recover at the beginning of a new frame, resulting in a
“tearing” of the image at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
