AD9879BS ,Mixed Signal Front End Set Top Box, Cable ModemGENERAL DESCRIPTION The 12-bit and 10-bit IF ADCs can convert direct IF inputs upThe AD9879 is a si ..
AD9879BSZ , Mixed-Signal Front End Set-Top Box, Cable Modem
AD9880KSTZ-100 , Analog/HDMI Dual Display Interface
AD9880KSTZ-100 , Analog/HDMI Dual Display Interface
AD9882AKSTZ-140 , Dual Interface for Flat Panel Displays
AD9882KST-100 ,Dual Interface for Flat Panel DisplaysGENERAL DESCRIPTION XC–DERTERMThe AD9882 offers designers the flexibility of an analog interfaceHSY ..
ADSP-21061KS-200 ,ADSP-2106x SHARC DSP Microcomputer FamilyApplications32-Bit Single-Precision and 40-Bit Extended-PrecisionSuper Harvard Architecture Compute ..
ADSP21061KS-200 ,ADSP-2106x SHARC DSP Microcomputer FamilyGENERAL DESCRIPTIONInterval TimerThe ADSP-21061 is a member of the powerful SHARC family1 Mbit On-C ..
ADSP-21061L ,SHARC, 44MHz, 150 MFLOPS, 3.3v, floating pointFEATURES1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)50 MIPS, 20 ns Instruction Rate, S ..
ADSP-21061LKB-160 ,ADSP-2106x SHARC DSP Microcomputer FamilySPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 18a. Synchronous REDY Timing ..
ADSP-21061-LKS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyGENERAL DESCRIPTIONInterval TimerThe ADSP-21061 is a member of the powerful SHARC family1 Mbit On-C ..
ADSP-21061LKS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)50 MIPS, 20 ns Instruction Rate, S ..
AD9879BS
Mixed Signal Front End Set Top Box, Cable Modem
REV. 0
Mixed-Signal Front End
Set-Top Box, Cable Modem
FEATURES
Low Cost 3.3 V MxFE™ for
DOCSIS EURO DOCSIS DVB DAVIC Compliant
Set-Top Box and Cable Modem Applications
232 MHz Quadrature Digital Upconverter
12-Bit Direct IF DAC (TxDAC+™)
Up to 65 MHz Carrier Frequency DDS
Programmable Sampling Clock Rates
16� Upsampling Interpolation LPF
Single-Tone Frequency Synthesis
Analog Tx Output Level Adjust
Direct Cable Amp Interface
12-Bit, 33 MSPS Direct IF ADC
with Optional Video Clamping Input
10-Bit, 33 MSPS Direct IF ADC
Dual 7-Bit, 16.5 MSPS Sampling I/Q ADC
12-Bit Sigma-Delta Auxiliary DAC
APPLICATIONS
Cable Modem and Satellite Systems
Set-Top Boxes
Power Line Modem
PC Multimedia
Digital Communications
Data and Video Modems
QAM, OFDM, FSK Modulation
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD9879 is a single-supply cable modem/set-top box mixed
signal front end. The device contains a transmit path interpolation
filter, a complete quadrature digital upconverter, and a transmit
DAC. The receive path contains a 12-bit ADC, a 10-bit ADC,
and dual 7-Bit ADCs. All internally required clocks and an output
system clock are generated by the PLL from a single crystal or
clock input.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth as high as 8.3 MHz.
Carrier frequencies up to 65 MHz with 26 bits of frequency tuning
resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits and can run at
sampling rates as high as 232 MSPS. Analog output scaling from
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
MxFE and TxDAC� are trademarks of Analog Devices, Inc.
The 12-bit and 10-bit IF ADCs can convert direct IF inputs up
to 70 MHz and run at sample rates up to 33 MSPS. A video
input with an adjustable signal clamping level, along with the
10-bit ADC, allow the AD9879 to process an NTSC and a
QAM channel simultaneously.
The programmable sigma-delta DAC can be used to control
external components, such as variable gain amplifiers (VGAs) or
voltage controlled tuners. The CA PORT provides an interface to
the AD8321/AD8323 or AD8322/AD8327 programmable gain
amplifier (PGA) cable drivers enabling host processor control via
the MxFE SPORT. The AD9879 is available in a 100-lead
MQFP package. It offers enhanced receive path undersampling
performance and lower cost when compared with the pin compat-
ible AD9873. The AD9879 is specified over the commercial
(–40°C to +85°C) temperature range.
AD9879–SPECIFICATIONSTx GAIN CONTROL
(VAS = 3.3 V � 5%, VDS = 3.3 V � 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz,
fMCLK = 54 MHz (M = 8), ADC Clock from OSCIN, RSET = 4.02 k�, 75 � DAC Load)*IQ ADC in Default Mode. ADC Clock Select Register 8, Bit 3 set to “0.”
AD987912-BIT ADC CHARACTERISTICS
AD9879
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9879 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Power Supply (VAVDD,VDVDD,VDRVDD) . . . . . . . . . . . . . .3.9 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . .5 mA
Digital Inputs . . . . . . . . . . . . . . . . .–0.3 V to VDRVDD + 0.3 V
Analog Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VAVDD + 0.3 V
Operating Temperature . . . . . . . . . . . . . . . . . –40ºC to +85ºC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150ºC
Storage Temperature . . . . . . . . . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . .300ºC
*Absolute Maximum Ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
ORDERING GUIDE
EXPLANATION OF TEST LEVELSDevices are 100% production tested at +25ºC and guaranteed
by design and characterization testing for commercial
operating temperature range (–40ºC to +85ºC).
II.Parameter is guaranteed by design and/or characterization
testing.
III.Parameter is a typical value only.
N/ATest level definition is not applicable.
THERMAL CHARACTERISTICS
Thermal Resistance100-Lead MQFP
�JA = 40.5ºC/W
AD9879
PIN CONFIGURATION
VIDEO INAGNDIF12+IF12–AGNDAVDDREFT12REFB12AVDDAGNDIF10+IF10–AGNDAVDDREFT10REFB10AVDDAGNDQ+Q–
TXIQ(1)TXIQ(0)
DVDD
DGND
DNC
PROFILE
RESET
DVDD
DGNDDGND
SCLK
SDIO
SDO
DGNDTX
DVDDTX
PWRDN
REFIO
FSADJ
AGNDTX
DNC
DNC
DNC
DNC
AGNDIQ
AVDDIQ
DRVDD
REFCLK
DRGND
DGND �-��-�_OUT
FLAG1
DVDD �-�
CA_EN
CA_DATA
CA_CLK
DVDDOSC
OSCIN
XTAL
DGNDOSC
AGNDPLL
PLLFILT
AVDDPLL
DVDDPLL
DGNDPLL
AVDDTX
TX+
TX–
DNC
DRGND
DRVDD
IF(11)
IF(10)
IF(9)
IF(8)
IF(7)
IF(6)
IF(5)
IF(4)
IF(3)
IF(2)
IF(1)
IF(0)
RXIQ(3)
RXIQ(2)
RXIQ(1)
RXIQ(0)
RXSYNC
DRGND
DRVDD
MCLK
DVDD
DGND
TXSYNC
TXIQ(5)
TXIQ(4)
TXIQ(3)
TXIQ(2)
PIN FUNCTION ASSIGNMENTS
AD9879
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity Error (DNL, NO MISSING CODES)An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024 codes,
respectively, must be present over all operating ranges.
Integral Nonlinearity Error (INL)Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
Phase NoiseSingle-sideband phase noise power is specified relative to the car-
rier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier.
Phase noise can be measured directly in single-tone transmit mode
with a spectrum analyzer that supports noise marker measure-
ments. It detects the relative power between the carrier and the
offset (1 kHz) sideband noise and takes the resolution bandwidth
(rbw) into account by subtracting 10log(rbw). It also adds a
correction factor that compensates for the implementation of the
resolution bandwidth, log display, and detector characteristic.
Output Compliance RangeThe range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Spurious-Free Dynamic Range (SFDR)The difference, in dB, between the rms amplitude of the DAC
output signal (or the ADC input signal) and the peak spurious
signal over the specified bandwidth (Nyquist bandwidth unless
otherwise noted).
Pipeline Delay (Latency)The number of clock cycles between conversion initiation and
the associated output data being made available.
Offset ErrorFirst transition should occur for an analog value 1/2 LSB above
–FS. Offset error is defined as the deviation of the actual transi-
tion from that point.
Gain ErrorThe first code transition should occur at an analog value 1/2 LSB
above full scale. The last transition should occur at an analog
value 1 1/2 LSB below the nominal full scale. Gain error is the
deviation of the actual difference between the first and last code
transitions and the ideal difference between the first and last
code transitions.
Aperture DelayThe aperture delay is a measure of the sample-and-hold ampli-
fier (SHA) performance and specifies the time delay between
the rising edge of the sampling clock input to when the input
signal is held for conversion.
Aperture Uncertainty (Jitter)Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the ADC.
Input Reference NoiseThe rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in LSB
and converted to an equivalent voltage. This results in a noise
figure that can directly be referred to the input of the MxFE.
Signal-To-Noise and Distortion (S/N+D, SINAD) RatioSINAD is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for SINAD is expressed in decibels.
Effective Number of Bits (ENOB)For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula:
N = (SINAD – 1.76)dB/6.02
it is possible to get a performance measurement expressed as N,
the effective number of bits. Thus, effective number of bits for a
device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Signal-To-Noise Ratio (SNR)SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Power Supply RejectionPower supply rejection specifies the converter’s maximum full-
scale change when the supplies are varied from nominal to
minimum and maximum specified voltages.
Channel-To-Channel Isolation (Crosstalk)In an ideal multichannel system, the signal in one channel will
not influence the signal level of another channel. The channel-
to-channel isolation specification is a measure of the change that
occurs to a grounded channel as a full-scale signal is applied to
another channel.
Table I.Register Map01h
02h
03h
08h
Register bits denoted with “0” MUST be programmed with a “0” every time that register is written.
AD9879
REGISTER BIT DEFINITIONS
Register 00 — Initialization
Bits 0 to 4: OSCIN MultiplierThis register field is used to program the on-chip multiplier
(PLL) that generates the chip’s high frequency system clock
fSYSCLK. The value of M will depend on the ADC clocking mode
selected as shown in the table below.
Table II.When using the AD9879 in systems where the Tx path and Rx
path do not operate simultaneously, the value of M can be pro-
grammed from 1 to 31. The maximum fSYSCLK rate of 236 MHz
must be observed, whatever value is chosen for M. When M is
set to 1, the internal PLL is disabled and all internal clocks are
derived directly from OSCIN.
Bit 5: ResetWriting a 1 to this bit resets the registers to their default values
and restarts the chip. The Reset bit always reads back 0. The
bits in Register 0 are not affected by this software reset. How-
ever, a low level at the RESET pin would force all registers,
including all bits in Register 0, to their default state.
Bit 6: SPI Bytes LSB FirstActive high indicates SPI serial port access of instruction byte
and data registers is least significant bit (LSB) first. Default low
indicates most significant bit (MSB) first format.
Bit 7: SDIO BidirectionalActive high configures the serial port as a three signal port with
the SDIO pin used as a bidirectional input/output pin. Default
low indicates the serial port uses four signals with SDIO config-
ured as an input and SDO configured as an output.
Register 01 — Clock Configuration
Bits 0 to 5: MCLK/REFCLK RatioThis bit field defines, R, the ratio between the auxiliary clock
output, REFCLK and MCLK. R can be any integer number
between 2 and 63. At default zero (R = 0), REFCLK provides a
buffered version of the OSCIN clock signal.
Bit 7: PLL Lock DetectWhen this bit is set low, the REFCLK pin functions in its default
mode, and provides an output clock with frequency fMCLK/R as
described above.
If this bit is set to 1, the REFCLK pin is configured to indicate
whether the PLL is locked to fOSCIN. In this mode, the REFCLK
pin should be low-pass filtered with an RC filter of 1.0 kW and
0.1 mF. A high output on REFCLK indicates that the PLL has
achieved lock with fOSCIN.
Register 02 — POWER-DOWNSections of the chip that are not used can be powered down
when the corresponding bits are set high. This register has a
default value of 0x00; all sections active.
Bit 2: Power-Down IF10 ADCActive high powers down the IF10 ADC.
Bit 3: Power-Down IF12 ADC ReferenceActive high powers down the 12-bit ADC reference.
Bit 4: Power-Down IF12 ADCActive high powers down the IF12 ADC.
Bit 5: Power-Down Digital TXActive high powers down the digital transmit section of the chip,
similar to the function of the PWRDN Pin.
Bit 6: Power-Down DAC TXActive high powers down the DAC.
Bit 7: Power-Down PLLActive high powers down the OSCIN multiplier.
Registers 03 and 04 — Sigma-Delta and Flag ControlThe sigma-delta control word is 12 bits wide and split in MSB bits
[11:4] and LSB bits [3:0]. Changes to the sigma-delta control
words take effect immediately for every MSB or LSB register
write. Sigma-delta output control words have a default value of
“0.” The control words are in straight binary format with 0x000
corresponding to the bottom of the scale and 0xFFF correspond-
ing to the top of the scale. See Figure 6 for details.
If the Flag 0 Enable (Register 3, Bit 0) is set high, the �-�_OUT
pin will maintain a fixed logic level determined directly by the
MSB of the sigma-delta control word.
The FLAG1 pin assumes the logic level programmed into the
FLAG1 bit (Register 3, Bit 1).
Register 07 —VIDEO INPUT CONFIGURATION
Bits 0-6: Clamp Level Control ValueThe 7-bit clamp level control value is used to set an offset to the
automatic clamp level control loop. The actual ADC output will
have a clamp level offset equal to 16 times the clamp level control
value as shown:
The default value for the clamp level control value is 0x20. This
results in an ADC output clamp level offset of 512 LSBs. The
valid programming range for the clamp level control value is
from 0x16 to 0x127.
Register 08 — ADC CLOCK CONFIGURATION
Bit 0: Send 10-Bit ADC Data OnlyWhen this bit is set high, the device enters a Nonmultiplexed
mode and only the data from the 10-bit ADC will be sent to the
IF [11:0] digital output port.
Bit 1: Send 12-Bit ADC Data OnlyWhen this bit is set high, the device enters a Nonmultiplexed
mode and only data from the 12-bit ADC will be sent to the IF
[11:0] digital output port.
Bit 3: Enable 7-Bits, IQ ADCWhen this bit is active the IQ ADC is put into 7-bit mode. In
this mode, the full-scale input range is 2 Vppd. When this bit is
set inactive, the IQ ADC is put into 6-bit mode and the full-
scale input voltage range is 1 Vppd.
Bit 4: Power-Down RXSYNC and IQ ADC Clocks
Bit 5: Rx Port Fast Edge RateSetting this bit to 1 increases the output drive strength of all
digital output pins, except MCLK, REFCLK, �-�_OUT, and
FLAG1. These pins always have high output drive capability.
Bit 7: ADC Clocked Direct from OSCINWhen set high, the input clock at OSCIN is used directly as the
ADC sampling clock. When set low, the internally generated
master clock, MCLK, is divided by two and used as the ADC
sampling clock. Best ADC performance is achieved when the
ADCs are sampled directly from fOSCIN using an external crystal
or low jitter crystal oscillator.
Register C—DIE REVISION
Bits 0 to 3: VersionThe die version of the chip can be read from this register.
Register D—Tx Frequency Tuning Words LSBsThis register accommodates two least significant bits for both of
the frequency tuning words. See description of Carrier Frequency
Tuning.
Register E—DAC Gain Control
Bits 0 to 3: DAC Fine Gain ControlThis bit field sets the DAC gain if the Tx Path AD8321/AD8323
Gain Control Select bit (Register F, Bit 3) is set to 0. The DAC
gain can be set from 0.0 dB to 7.5 dB in increments of 0.5 dB.
Table III details the programming.
Table III.
Register F — Tx PATH CONFIGURATION
Bit 0: Tx Path Transmit Single ToneActive high configures the AD9879 for single-tone applications
(e.g., FSK). The AD9879 will supply a single frequency output
as determined by the frequency tuning word selected by the
active profile. In this mode, the TXIQ input data pins are ignored
but should be tied to a valid logic voltage level. Default value is
0 (inactive).
Bit 1: Tx Path Spectral InversionWhen set to 1, inverted modulation is performed:
Default is logic zero, noninverted modulation:
Bit 2: Tx Path Bypass Sinc–1 FilterSetting this bit high bypasses the digital inverse sinc filter of the
Tx path.
Bit 3: Tx Path AD8322/AD8327 Gain Control Modecontrol select changes the interpretation of the bits in Registers
13 and 17. See Cable Driver Gain Control.
Bit 5: Tx Path Select Profile 1The AD9879 quadrature digital upconverter is capable of stor-
ing two preconfigured modulation modes called profiles.
Each profile defines a transmit frequency tuning word and cable
driver amplifier gain (/DAC gain) setting. The Profile Select bit
or PROFILE pin programs the current register profile to be used.
The Profile Select bit should always be “0” if the PROFILE pin
is to be used to switch between profiles. Using the Profile Select
bit as a means of switching between different profiles requires
the PROFILE pin to be tied low.
Registers 10–17: Carrier Frequency Tuning
Tx Path Frequency Tuning WordsThe frequency tuning word (FTW) determines the DDS-generated
carrier frequency (fC) and is formed via a concatenation of
register addresses.
The 26-bit FTW is spread over four register addresses. Bit 25 is
the MSB and Bit 0 is the LSB.
The carrier frequency equation is given as:
Changes to FTW bytes take effect immediately.
Cable Driver Gain ControlThe AD9879 has a 3-pin interface to the AD832x family of
programmable gain cable driver amplifiers. This allows direct
control of the cable driver’s gain through the AD9879.
In its Default mode, the complete 8-bit register value is transmitted
over the 3-wire cable amplifier (CA) interface.
If Bit 3 of Register F is set high, Bits [7:4] determine the 8-bit
word sent over the CA interface according to Table IV.
Table IV.In this mode, the lower bits determine the fine gain setting
of the DAC output.
Table V.New data is automatically sent over the 3-wire CA interface
(and DAC gain adjust) whenever the value of the active gain
AD9879The formula for the combined output level calculation of the
AD9879 fine gain and AD8327 or AD8322 coarse gain is:
with:
fine = decimal value of Bits [3:0]
coarse = decimal value of Bits [7:8]
V9877(0): Level at AD9879 output in dBmV for fine = 0.
V8327: Level at output of AD8327 in dBmV.
V8322: Level at output of AD8322 in dBmV.
DEVICE OVERVIEWTo gain a general understanding of the AD9879, it is helpful to
refer to Figure 1, which displays a block diagram of the device
architecture. The device consists of a transmit path, receive path,
and auxiliary functions, such as a DPLL, a sigma-delta DAC,serial control port, and a cable amplifier interface.
Transmit PathThe transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a
CA_PORT12-bit current output DAC. The maximum output current of the
DAC is set by an external resistor. The Tx output PGA provides
additional transmit signal level control.
The transmit path interpolation filter provides an upsampling
factor of 16 with an output signal bandwidth as high as 5.8 MHz.
Carrier frequencies up to 65 MHz with 26 bits of frequency
tuning resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits and can run at
sampling rates as high as 232 MSPS.
Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is
available to preserve SNR when reduced output levels are required.
Data AssemblerThe AD9879 data path operates on two 12-bit words, the I and Q
components, that form a complex symbol. The data assembler
builds the 24-bit complex symbols from four consecutive 6-bit
nibbles read over the TxIQ[5:0] bus. The nibbles are strobed
synchronous to the master clock, MCLK, into the data assembler.
A high level on TxSYNC signals the start of a transmit symbol.
The first two nibbles of the symbol form the I component, the
second two nibbles form the Q component. Symbol components
are assumed to be in twos complement format. The timing of
the interface is fully described in the Transmit Timing section
of this data sheet.
