AD9874BST ,IF Digitizing SubsystemSPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V,1VDDQ = VDDP = 2.7 V ..
AD9876BST ,Broadband Modem Mixed-Signal Front Endapplications. dynamic performance with low power consumption.Also on-chip is a PLL clock multiplier ..
AD9877ABS ,Single Supply Cable Modem/Set Top Box Mixed Signal Front EndGENERAL DESCRIPTION The 12-bit ADC has excellent undersampling performance,The AD9877 is a single-s ..
AD9878BSTZ ,Mixed-Signal Front End for Broadband ApplicationsGENERAL DESCRIPTION The AD9878 is a single-supply, cable modem/set-top box, The 12-bit ADCs provide ..
AD9879BS ,Mixed Signal Front End Set Top Box, Cable ModemGENERAL DESCRIPTION The 12-bit and 10-bit IF ADCs can convert direct IF inputs upThe AD9879 is a si ..
AD9879BSZ , Mixed-Signal Front End Set-Top Box, Cable Modem
ADSP-21060LKS-160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeaturesof the ADSP-21000 family core. The ADSP-21060 is code- andfunction-compatible with the ADSP ..
ADSP21060LKS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilySPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17Figure 18a. Synchronous REDY Timing ..
ADSP-21061 ,SHARC, 50 MHz, 150 MFLOPS, 5v, floating pointSPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 18a. Synchronous REDY Timing ..
ADSP-21061KS-133 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 7. JTAG Clocktree for Multipl ..
ADSP-21061KS-160 ,ADSP-2106x SHARC DSP Microcomputer Familyapplications. The ADSP-21061 com-Serial Portsbines the ADSP-21000 DSP core with a dual-ported on-ch ..
ADSP-21061KS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 7. JTAG Clocktree for Multipl ..
AD9874BST
IF Digitizing Subsystem
REV. 0
IF Digitizing Subsystem*. Patent No. 5,969,657; other patents pending.
FEATURES
10 MHz–300 MHz Input Frequency
6.8 kHz–270 kHz Output Signal Bandwidth
8.1 dB SSB NF
0 dBm IIP3
AGC Free Range up to –34 dBm
12 dB Continuous AGC Range
16 dB Front End Attenuator
Baseband I/Q 16-bit (or 24-bit) Serial Digital Output
LO and Sampling Clock Synthesizers
Programmable Decimation Factor, Output Format,
AGC, and Synthesizer Settings
370 � Input Impedance
2.7 V–3.6 V Supply Voltage
Low Current Consumption: 20 mA
48–Lead LQFP Package (1.4 mm Thick)
APPLICATIONS
Multimode Narrowband Radio Products
Analog/Digital UHF/VHF FDMA Receivers
TETRA, APCO25, GSM/EDGE
Portable and Mobile Radio Products
Base Station Applications
GENERAL DESCRIPTIONThe AD9874 is a general-purpose IF subsystem that digitizes a
low level 10 MHz–300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874
consists of a low noise amplifier, a mixer, a band-pass sigma-delta
analog-to-digital converter, and a decimation filter with program-
mable decimation factor. An automatic gain control (AGC) circuit
gives the AD9874 12 dB of continuous gain adjustment. Auxiliary
blocks include both clock and LO synthesizers.
The AD9874’s high dynamic range and inherent antialiasing
provided by the band-pass sigma-delta converter allow the
AD9874 to cope with blocking signals up to 95 dB stronger
than the desired signal. This attribute can often reduce the cost of
a radio by reducing its IF filtering requirements. Also, it enables
multimode radios of varying channel bandwidths, allowing the
IF filter to be specified for the largest channel bandwidth.
The SPI port programs numerous parameters of the AD9874,
thus allowing the device to be optimized for any given
application. Programmable parameters include the following:
synthesizer divide ratios; AGC attenuation and attack/decay
time; the received signal strength level; decimation factor; the
output data format; 16dB attenuator; and the selected bias
currents. The bias currents of the LNA and mixer can be further
reduced at the expense of the degraded performance for battery-
powered applications.
FUNCTIONAL BLOCK DIAGRAM
LO SYNTHESIZER
NOTESStandard operating mode: LNA/Mixer @ high bias setting, VGA @ Min ATTEN setting, synthesizers in normal (not fast acquire) mode, fCLK = 18 MHz, decimation
factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.This includes 0.9 dB loss of matching network.AGC with DVGA enabled.Measured in 10 kHz bandwidth.Programmable in 0.67 mA steps.Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V,
VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted.)1AD9874–SPECIFICATIONS
AD9874
DIGITAL SPECIFICATIONS(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V,
fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted.)1SPI-WRITE OPERATION
CMOS LOGIC INPUTS
NOTES
1Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, fCLK = 18 MHz, decimation factor = 300, 10 pF load on SSI output pins:
VDDx = 3.0 V.
2Programmable in steps of 48 or 60.
3CMOS output mode with CLOAD = 10 pF and Drive Strength = 7.
4Absolute Max and Min input/output levels are VDDH +0.3 V and –0.3 V.
5IOL = 1 mA; specification is also dependent on Drive Strength setting.
Specifications subject to change without notice.
AD9874
ABSOLUTE MAXIMUM RATINGS**Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
EXPLANATION OF TEST LEVELS
TEST LEVEL100% production tested.
II.100% production tested at 25°C and sample tested at specified
temperatures. AC testing done on sample basis.
III.Sample tested only.
IV.Parameter is guaranteed by design and/or characterization testing.Parameter is a typical value only.
VI.All devices are 100% production tested at 25°C; min. and max.
guaranteed by design and characterization for industrial
temperature range.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9874 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
THERMAL CHARACTERISTICS
Thermal Resistance48-Lead LQFP
θJA = 76.2°C/W
θJC = 17°C/W
ORDERING GUIDE
PIN CONFIGURATION
GNDL
FREF
GNDS
SYNCB
GNDH
DOUTB
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
DOUTA
CLKOUT
VDDH
VDDD
VREFNPE
VDDIIFINCXIFGNDICXVLLOPLONCXVMVDDLVDDPIOUTLGNDP
RREF
VDDQ
IOUTC
GNDQ
VDDC
GNDC
CLKPCLKN
GNDSGNDDPD
PIN FUNCTION DESCRIPTIONSAD9874
DEFINITION OF SPECIFICATIONS/TEST METHODS
Single-Sideband Noise Figure (SSB NF)Noise figure (NF) is defined as the degradation in SNR perfor-
mance (in dB) of an IF input signal after it passes through a
component or system. It can be expressed with the following
equation:
The term SSB is applicable for heterodyne systems containing a
mixer. It indicates that the desired signal spectrum resides on
only one side of the LO frequency (i.e. single sideband); thus a
“noiseless” mixer has a noise figure of 3 dB.
The AD9874’s SSB noise figure is determined by the following
equation:
where PIN is the input power of an unmodulated carrier, BW is
the noise measurement bandwidth, –174 dBm/Hz is the thermal
noise floor at 293°K, and SNR is the measured signal-to-noise
ratio in dB of the AD9874.
Note, PIN is set to –85 dBm to minimize any degradation in
measured SNR due to phase noise from the RF and LO signal
generators. The IF frequency, CLK frequency, and decimation
factors are selected to minimize any “spurious” components
falling within the measurement bandwidth. Note, a bandwidth
of 10 kHz is used for the data sheet specification on Page 2.
Refer to Figures 22a and 22b for an indication of how NF varies
with BW. Also, refer to the TPCs to see how NF is affected by
different operating conditions. All references to noise figures
within this data sheet imply single-sideband noise figure.
Input Third Order Intercept (IIP3)IIP3 is a figure of merit to determine a component’s or system’s
susceptibility to intermodulation distortion (IMD) from its third
order nonlinearities. Two unmodulated carriers’ at a specified
frequency relationship (f1 and f2) are injected into a nonlinear
system exhibiting third order nonlinearities producing IMD
components at 2f1 – f2 and 2f2 – f1. IIP3 graphically represents
the extrapolated intersection of the carrier’s input power with
the third order IMD component when plotted in dB. The dif-
ference in power (D in dBc) between the two carriers and the
resulting third order IMD components can be determined from
Dynamic Range (DR)Dynamic range is the measure of a small target input signal
(PTARGET) in the presence of a large unwanted interferer signal
(PINTER). Typically, the large signal will cause some unwanted
characteristic of the component or system to degrade, thus making
it unable to detect the smaller target signal correctly. In the case of
the AD9874, it is often a degradation in Noise Figure at increased
VGA attenuation settings that limits its dynamic range (refer to
TPC 15a, 15b, and 15c).
The test method for the AD9874 is as follows. The small target
signal (an unmodulated carrier) is input at the center of the IF
frequency and its power level (PTARGET) is adjusted to achieve an
SNRTARGET of 6 dB. The power of the signal is then increased by
3 dB prior to injecting the interferer signal. The offset frequency
of the interferer signal is selected so that aliases produced by the
decimation filter’s response as well as phase noise from the LO
(due to reciprocal mixing) do not fall back within the measure-
ment bandwidth. For this reason, an offset of 110 kHz was
selected. The interferer signal (also an unmodulated carrier) is
then injected into the input and its power level is increased to the
point (PINTER) where the target signal SNR is reduced to 6dB.
Note, the AD9874’s AGC is enabled for this test.
IF Input Clip PointThe IF input clip point is defined to be 2 dB below the input
power level (PIN), resulting in the “clipping” of the AD9874’s
ADC. Unlike other linear components that typically exhibit a
“soft” compression (characterized by its 1 dB compression point),
an ADC exhibits a “hard” compression once its input signal
exceeds its rated maximum input signal range. In the case of the
AD9874, which contains a �-� ADC, “hard” compression
should be avoided since it causes severe SNR degradation.
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25�C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1TPC 1a.CDF of SSB Noise Figure
(VDDx = 3.0 V, High Bias2)
TPC 2a.CDF of IIP3 (VDDx = 3.0 V,
High Bias2)
TPC 3a.CDF of Dynamic Range
(VDDx = 3.0 V, High Bias2)
TPC 1b.SSB Noise Figure vs. Supply
(High Bias2)
TPC 2b.IIP3 vs. Supply (High Bias2)
TPC 3b.Dynamic Range vs. Supply
(High Bias2)
TPC 1c.SSB Noise Figure vs. Supply
(Low Bias3)
TPC 2c.IIIP3 vs. Supply (Low Bias3)
TPC 3c.Dynamic Range vs. Supply
(Low Bias3)
AD9874
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25�C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1TPC 4a.CDF of Maximum VGA
Attenuation “Clip Point” (VDDx = 3.0 V,
High Bias2)
TPC 5a.CDF of Minimum VGA
Attenuation “Clip Point” (VDDx = 3.0V,
High Bias2)
TPC 6a.CDF of Supply Current2
TPC 4b.Maximum VGA Attenuation
“Clip Point” vs. Supply (High Bias2)
TPC 5b.Minimium VGA Attenuation
“Clip Point” vs. Supply (High Bias2)
TPC 6b.Supply Current vs. fCLK2
TPC 4c.Maximum VGA Attenuation
“Clip Point” vs. Supply (Low Bias3)
TPC 5c.Minimium VGA Attenuation
“Clip Point” vs. Supply (Low Bias3)
TPC 6c.Supply Current vs. Supply2
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25�C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1TPC 7a.Normalized Gain Variation
vs. LO Drive (VDDx = 3.0 V)
TPC 8a.Complex FFT of Baseband
I/Q for Single-Tone (High Bias)
TPC 9a.Complex FFT of Baseband
I/Q for Dual Tone IMD (High Bias
with each IFIN Tone @ –35 dBm)
TPC 7b.Noise Figure and IMD
vs. LO Drive (VDDx = 3.0 V)
TPC 8b.Gain Compression vs. IFIN
(High Bias2)
TPC 9b.IMD vs. IFIN (High Bias2)
TPC 7c.Gain Compression vs. IFIN
with 16 dB LNA Attenuator Enabled
TPC 8c. Gain Compression vs. IFIN
(Low Bias3)
TPC 9c.IMD vs. IFIN (Low Bias3)
AD9874
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25�C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1TPC 10a.Noise Figure vs. BW (Mini-
mum Attenuation, fCLK = 13 MSPS)
TPC 11a.Noise Figure vs. VGA
Attenuation (fCLK = 13 MSPS)
TPC 12a.IMD vs. IFIN (fCLK = 13 MSPS)
TPC 10b.Noise Figure vs. BW (Mini-
mum Attenuation, fCLK = 18 MSPS)
TPC 11b.Noise Figure vs. VGA
Attenuation (fCLK = 18 MSPS)
TPC 12b. IMD vs. IFIN (fCLK = 18 MSPS)
TPC 10c.Noise Figure vs. BW (Mini-
mum Attenuation, fCLK = 26 MSPS)
TPC 11c.Noise Figure vs. VGA
Attenuation (fCLK = 26 MSPS)
TPC 12c.IMD vs. IFIN (fCLK = 26 MSPS)
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25�C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1TPC 13a.Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 18 MSPS,
BW = 10 kHz, High Bias)
TPC 14a.Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 26 MSPS,
BW = 24 kHz, High Bias)
TPC 15a.Noise Figure vs. Interferer
Level (16-Bit Data, BW = 12.5 kHz,
AGCR = 1, finterferer = fIF + 110 kHz)
TPC 13b. Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 18 MSPS,
BW = 10 kHz, Low Bias)
TPC 14b. Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 26 MSPS,
BW = 24 kHz, Low Bias)
TPC 15b.Noise Figure vs. Interferer
Level (16-Bit Data with DVGA,
BW = 12.5 kHz, AGCR = 1,
TPC 13c.Input IP3 vs. Frequency
(fCLK = 18 MSPS)
TPC 14c.Input IP3 vs. Frequency
(fCLK = 26 MSPS)
TPC 15c.Noise Figure vs. Interferer
Level (24-Bit Data, BW = 12.5 kHz,
AGCR = 1, finterferer = fIF + 110 kHz)
AD9874
SERIAL PERIPHERAL INTERFACE (SPI)The serial peripheral interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed
below as well as to read back their contents. TableI provides a list of the registers that may be programmed through the SPI port.
Addresses and default values are given in hexadecimal form.
Table I.SPI Address MapPOWER CONTROL REGISTERS
AGC
DECIMATION FACTOR
LO SYNTHESIZER
CLOCK SYNTHESIZER
0x14
SSI CONTROL
ADC TUNING
TEST REGISTERS AND SPI PORT READ ENABLE
Table I.SPI Address Map (continued)
AD9874
SERIAL PORT INTERFACE (SPI)The serial port of the AD9874 has 3-wire or 4-wire SPI capa-
bility, allowing read/write access to all registers that configure the
device’s internal parameters. The default 3-wire serial commu-
nication port consists of a clock (PC), peripheral enable (PE),
and a bidirectional data (PD) signal. The inputs to PC, PE, and
PD contain a Schmitt trigger with a nominal hysteresis of 0.4V
centered about the digital interface supply (i.e., VDDH/2).
A 4-wire SPI interface can be enabled by setting the MSB of the
SSICRB register ( Reg. 0x19, Bit 7) resulting in the output data
also appearing on the DOUTB Pin. Note, since the default
power-up state sets DOUTB low, bus contention is possible for
systems sharing the SPI output line. To avoid any bus contention,
the DOUTB Pin can be three-stated by setting the fourth control
bit in the three-state bit (Reg 0x3B, Bit 3). This bit can then be
toggled to gain access to the shared SPI output line.
An 8-bit instruction header must accompany each read and write
SPI operation. Only the write operation supports an auto-increment
mode allowing the entire chip to be configured in a single write
operation. The instruction header is shown in Table I. It includes
a read/not-write indicator bit, 6 address bits, and a Don’t Care
bit. The data bits immediately follow the instruction header for
both read and write operations. Note, address and data are
always given MSB first.
Table II. Instruction Header Information
MSBLSBFigure 1a illustrates the timing requirements for a write operation
to the SPI port. After the peripheral enable (PE) signal goes
low, data (PD) pertaining to the instruction header is read on
the rising edges of the clock (PC). To initiate a write operation,
the read/not-write bit is set low. After the instruction header is
read, the eight data bits pertaining to the specified register are
shifted into the data pin (PD) on the rising edge of the next
eight clock cycles. PE stays low during the operation and goes
high at the end of the transfer. If PE rises before the eightclock
cycles have passed, the operation is aborted.
If PE stays low for an additional eight clock cycles, the destination
address is incremented and another eight bits of data are shifted
in. Again, should PE rise early, the current byte is ignored. By using
this implicit addressing mode, the entire chip can be configured
with a single write operation. Registers identified as being subject
to frequent updates, namely those associated with power control
and AGC operation, have been assigned adjacent addresses to
minimize the time required to update them. Note, multibyte registers
are “big-endian” (the most significant byte has the lower address)
and are updated when a write to the least significant byte occurs.
Figure 1b illustrates the timing for a read operation to the SPI port.
Although the AD9874 does not require read access for proper
operation, it is often useful in the product development phase or
for system authentication. Note, the readback enable bit (Register
0x3A, Bit 3) must be set for a read operation with a 3-wire SPI
interface. After the peripheral enable (PE) signal goes low, data
(PD) pertaining to the instruction header is read on the rising
edges of the clock (PC). A read operation occurs if the read/not-
write indicator is set high. After the address bits of the instruction
header are read, the eight data bits pertaining to the specified
register are shifted out of the data pin (PD) on the falling edges of
the next eight clock cycles. If the 4-wire SPI interface is enabled,
the eight data bits will also appear on the DOUTB Pin with the
same timing relationship as those appearing at PD. After the last
data bit is shifted out, the user should return PE high, causing PD
to become three-stated and return to its normal status as an input
pin. Since the auto-increment mode is not supported for read
operations, an instruction header is required for each register read
operation and PE must return high before initiating the next read
operation.
Figure 1a.SPI Write Operation Timing
SYNCHRONOUS SERIAL INTERFACE (SSI)The AD9874 provides a high degree of programmability of its
SSI output data format, control signals, and timing parameters
to accommodate various digital interfaces. In a 3-wire digital
interface, the AD9874 provides a frame sync signal (FS), a
clock output (CLKOUT), and a serial data stream (DOUTA)
signal to the host device. In a 2-wire interface, the frame sync
information is embedded into the data stream, thus only a
CLKOUT and DOUTA output signal are provided to the host
device. The SSI control registers are SSICRA, SSICRB, and
SSIORD. Table III shows the different bit fields associated with
these registers.
The primary output of the AD9874 is the converted I and Q
demodulated signal available from the SSI port as a serial bit
stream contained within a frame. The output frame rate is equal
to the modulator clock frequency (fCLK) divided by the digital
filter’s decimation factor that is programmed in the Decimator
Register (0x07). The bit stream consists of an I word followed
by a Q word, where each word is either 24 bits or 16 bits long
and is given MSB first in two’s complement form. Two optional
bytes may also be included within the SSI frame following the
Qword. One byte contains the AGC attenuation and the other
byte contains both a count of modulator reset events and an
estimate of the received signal amplitude (relative to full scale
of the AD9874’s ADC). Figure 2 illustrates the structure of the
SSI data frames in a number of SSI modes.
Figure 2.SSI Frame Structure
The two optional bytes are output if the EAGC bit of SSICRA
is set. The first byte contains the 8-bit attenuation setting (0 = no
attenuation, 255 = 24 dB of attenuation), while the second byte
contains a 2-bit reset field and 6-bit received signal strength
signal field. The reset field contains the number of modulator
reset events since the last report, saturating at 3. The received
signal strength (RSSI) field is a linear estimate of the signal
strength at the output of the first decimation stage; 60 corresponds
to a full-scale signal.
The two optional bytes follow the I and Q data as a 16-bit word
providing that the AAGC bit of SSICRA is not set. If the
AAGC bit is set, the two bytes follow the I and Q data in an
alternating fashion. In this alternate AGC data mode, the LSB
of the byte containing the AGC attenuation is a 0, while the LSB
of the byte containing reset and RSSI information is always a 1.
In a 2-wire interface, the embedded frame sync bit (EFS) within
the SSICRA Register is set to 1. In this mode, the framing infor-
mation is embedded in the data stream with each eight bits of
data surrounded by a start bit (low) and a stop bit (high), and
each frame ends with at least 10 high bits. FS remains either
low or three-stated (default) depending on the state of the
SFST bit. Other control bits can be used to invert the frame
sync (SFSI), to delay the frame sync pulse by one clock
period (SLFS), to invert the clock (SCKI), or to three-state the
clock (SCKT). Note that if EFS is set, SLFS is a don’t care.
The SSIORD Register controls the output bit rate (fCLKOUT) of
the serial bit stream. fCLKOUT can be set to equal the modulator
clock frequency (fCLK) or an integer fraction of it. It is equal to
fCLK divided by the contents of the SSIORD Register. Note,
fCLKOUT should be chosen such that it does not introduce harmful
spurs within the pass band of the target signal. Users must verify
that the output bit rate is sufficient to accommodate the required
number of bits per frame for a selected word size and decimation
factor. Idle (high) bits are used to fill out each frame.
Table III.SSI Control Registers
AD9874
Table IV.Number of Bits per Frame for Different
SSICR Settings*The number of bits per frame with embedded frame sync (EFS = 1) assume at
least 10 idle bits are desired.
The maximum SSIORD setting can be determined by the
following equation:
where TRUNC is the truncated integer value.
Table IV lists the number of bits within a frame for 16-bit and
24-bit output data formats for all of the different SSICR settings.
The decimation factor is determined by the contents of
Register 0x07.
An example helps illustrate how the maximum SSIORD setting
is determined. Suppose a user selects a decimation factor of 600
(Register 0x07, K = 0, M = 9) and prefers a 3-wire interface
with a dedicated frame sync (EFS = 0) containing 24-bit data
(DW = 1) with nonalternating embedded AGC data included
(EAGC = 1, AAGC = 0). Referring to TableIV, each frame will
consist of 64 data bits. Using Equation 1, the maximum
SSIORD setting is 9 (= TRUNC(600/64)). Thus, the user can
select any SSIORD setting between 1 and 9.
Figure 3a illustrates the output timing of the SSI port for several
SSI control register settings with 16-bit I/Q data, while Figure3b
shows the associated timing parameters. Note, the same timing
relationship holds for 24-bit I/Q data, with the exception that I and
Qword lengths now become 24 bits. In the default mode of the
operation, data is shifted out on rising edges of CLKOUT after a
pulse equal to a clock period is output from the Frame Sync (FS)
Pin. As described above, the output data consists of a 16- or 24-bit
I sample followed by a 16- or 24-bit Q sample, plus two optional
bytes containing AGC and status information.
Figure 3b. Timing Parameters for SSI Timing*
*Timing parameters also apply to inverted CLKOUT or FS modes with tDV
relative to the falling edge of the CLK and/or FS.
The AD9874 also provides the means for controlling the switching
characteristics of the digital output signals via the DS (drive
strength) field of the SSICRB. This feature is useful in limiting
switching transients and noise from the digital output that may
ultimately couple back into the analog signal path, potentially
degrading the AD9874’s sensitivity performance. Figures 3c and
3d show how the NF can vary as a function of the SSI setting for
an IF frequency of 109.65 MHz. The following two observations
can be made from these figures:The NF becomes more sensitive to the SSI output drive strength
level at higher signal bandwidth settings.The NF is dependent on the number of bits within an SSI frame,
becoming more sensitive to the SSI output drive strength level
as the number of bits is increased. As a result, one should select
the lowest possible SSI drive strength setting that still meets
the SSI timing requirements.
Figure 3c. NF vs. SSI Output Drive Strength
(VDDx = 3.0 V, fCLK = 18 MSPS, BW = 10 kHz)
Figure 3d. NF vs. SSI Output Drive Strength
(VDDx = 3.0 V, fCLK = 18 MSPS, BW = 75 kHz)
Table V lists the typical output rise/fall times as a function of
DS for a 10pF load. Rise/fall times for other capacitor loads can
be determined by multiplying the typical values presented in
TableV by a scaling factor equal to the desired capacitive load
Table V.Typical Rise/Fall times (±25 %) with a 10 pF
Capacitive Load for Each DS Setting
SynchronizationApplications, such as receiver diversity, employing more than
one AD9874 device may desire synchronization of the digital
output data. SYNCB can be used for this purpose and applied
upon system initialization. It is an active-low signal that clears
the clock counters in both the decimation filter and the SSI
port. The counters in the clock synthesizers are not reset, since
it is presumed that the CLK signals of multiple chips would be
connected together. SYNCB also clears the registers in the
decimation filter and resets the modulator. As a result, valid
data representative of the input signal will be available once the
digital filters have been flushed.
Figure 4a shows the timing relationship between SYNCB and the
SSI port’s CLKOUT and FS signals. SYNCB is an asynchronous
active-low signal that must remain low for at least half an input
clock period (i.e., 1/(2 × fCLK) ). CLKOUT returns high while
FS remains low upon SYNCB going low. CLKOUT will become
active within 1 to 2 output clock periods upon SYNCB returning
high. FS will reappear several output clock cycles later, depend-
ing on the digital filter’s decimation factor and the SSIORD
setting. To verify proper synchronization, the FS signals of the
multiple AD9874 devices should be monitored.
Figure 4a.SYNCB Timing
INTERFACING TO DSPsThe AD9874 connects directly to an Analog Devices program-
mable digital signal processor (DSP). Figure 4b illustrates an
example with the Blackfin® series of ADSP-2153x processors.
The Blackfin DSP series is a family of 16-bit products optimized
for telecommunications applications with its dynamic power
management feature making it well suited for portable radio
products. The code compatible family members share the funda-
mental core attributes of high performance, low power consumption,
and the ease-of-use advantages of microcontroller instruction set.
AD9874Figure 4b.Example of AD9874 and ADSP-2153x Interface
As shown in Figure 4b, AD9874’s synchronous serial interface
(SSI) links the receive data stream to the DSP’s Serial Port (SPORT).
For AD9874 set-up and register programming, the device connects
directly to ADSP-2153x’s SPI-PORT. Dedicated select lines (SEL)
allow the ADSP-2153x to program and read back registers of
multiple devices using only one SPI port. The DSP driver code
pertaining to this interface is available on the AD9874 web page
(http://products.analog.com/products/info.aspproduct=AD9874).
POWER CONTROLTo allow power consumption to be minimized, the AD9874
possesses numerous SPI-programmable power-down and bias
control bits. The AD9874 powers up with all of its functional
blocks placed into a standby state (i.e., STBY Register default is
0xFF). Each major block may then be powered up by writing a0
to the appropriate bit of the STBY Register. This scheme provides
the greatest flexibility for configuring the IC to a specific appli-
cation as well as for tailoring the IC’s power-down and wake-up
characteristics. Table VI summarizes the function of each of the
STBY bits. Note, when all the blocks are in standby, the master
reference circuit is also put into standby and thus the current is
reduced by a further 0.4 mA.
Table VI.Standby Control Bits
STBY6:LO
3:GC
NOTES
The AD9874 also allows control over the bias current in the LNA,
mixer, and clock oscillator. The effects on current consumption
and system performance are described in the section dealing
with the affected block.
LO SynthesizerThe LO Synthesizer shown in Figure 5 is a fully programmable
PLL capable of 6.25kHz resolution at input frequencies up to
300MHz and reference clocks of up to 25MHz. It consists of a
low noise digital phase-frequency detector (PFD), a variable
output current charge pump (CP), a 14-bit reference divider,
programmable A and B counters, and a dual-modulus 8/9 prescaler.
The A (3-bit) and B (13-bit) counters, in conjunction with the
dual 8/9 modulus prescaler, implement an N divider with N =
8 � B + A. In addition, the 14-bit reference counter (R Counter)
allows selectable input reference frequencies, fREF, at the PFD
input. A complete PLL (phase-locked loop) can be implemented
if the synthesizer is used with an external loop filter and VCO
(voltage controlled oscillator).
The A, B, and R counters can be programmed via the following
registers: LOA, LOB, and LOR. The charge pump output current
is programmable via the LOI Register from 0.625mA to 5.0mA(2)
An on-chip fast acquire function (enabled by the LOF bit)
automatically increases the output current for faster settling
during channel changes. The synthesizer may also be disabled
using the LO standby bit located in the STBY Register.
Figure 5.LO Synthesizer
The LO (and CLK) synthesizer works in the following manner.
The externally supplied reference frequency, fREF, is buffered and
divided by the value held in the R counter. The internal fREF is
then compared to a divided version of the VCO frequency, fLO.
The phase/frequency detector provides UP and DOWN pulses
whose widths vary depending upon the difference in phase and
frequency of its two input signals. The UP/DOWN pulses con-
trol the charge pump making current available to charge the
external low-pass loop filter when there is a discrepancy between
the inputs of the PFD. The output of the low-pass filter feeds an
external VCO whose output frequency, fLO, is driven such that
its divided down version, fLO, matches that of fREF, thus closing
the feedback loop.
The synthesized frequency is related to the reference frequency
and the LO Register contents as follows:
An example may help illustrate how the values of LOA, LOB, and
LOR can be selected. Consider an application employing a 13MHz
crystal oscillator (i.e., fREF = 13 MHz) with the requirement that
fREF = 100 kHz and fLO = 143 MHz (i.e., high side injection with
fIF = 140.75 MHz and fCLK = 18 MSPS). LOR is selected to be
130 such that fREF = 100 kHz. The N-divider factor is 1430,
which can be realized by selecting LOB = 178 and LOA =6.
The stability, phase noise, spur performance, and transient
response of the AD9874’s LO (and CLK) synthesizers are deter-
mined by the external loop filter, the VCO, the N-divide factor,
and the reference frequency, FREF. A good overview of the
theory and practical implementation of PLL synthesizers (fea-
tured as a three-part series in Analog Dialogue) can be found at:/library/analogDialogue/archives/33-03/phase/
index.html/library/analogDialogue/archives/33-05/
phase_locked/index.html/library/analogDialogue/archives/33-07/
phase3/index.html
Also, a free software copy of the Analog Devices ADIsimPLL,
a PLL synthesizer simulation tool, is available at /
technology/RFComms/rfif/ADIsimPLL.html. Note, the ADF4112
model can be used as a close approximation to the AD9874’s
LO synthesizer when using this software tool.
Figure 6.Equivalent Input of LO and REF Buffers
Figure 6 shows the equivalent input structures of the synthesiz-
ers’ LO and REF buffers (excluding the ESD structures). The
LO input is fed to the LO synthesizer’s buffer as well as the
AD9874’s mixer’s LO port. Both inputs are self-biasing and
thus tolerate ac-coupled inputs. The LO input can be driven
with a single-ended or differential signal. Single-ended dc-
coupled inputs should ensure sufficient signal swing above and
below the common-mode bias of the LO and REF buffers
(i.e., 1.75 V and VDDL/2). Note, the FREF input is slew rate
dependent and must be driven with input signals exceeding
6.4 V/msec to ensure synthesizer operation.
Fast Acquire ModeThe fast acquire circuit attempts to boost the output current when
the phase difference between the divided-down LO (i.e., fLO)
and the divided-down reference frequency (i.e., fREF) exceeds the
threshold determined by the LOFA Register. The LOFA Register
specifies a divisor for the fREF signal that determines the period
(T) of this divided-down clock. This period defines the time
interval used in the fast acquire algorithm to control the charge
pump current.
Assume for the moment that the nominal charge pump current
is at its lowest setting (i.e., LOI = 0) and denote this minimum
current by I0. When the output pulse from the phase comparator
exceeds T, the output current for the next pulse is 2 I0. When
the pulse is wider than 2 T, the output current for the next pulse is
3 I0, and so forth, up to eight times the minimum output current.
If the nominal charge pump current is more than the minimum
value (i.e., LOI > 0), the preceding rule is only applied if it results
in an increase in the instantaneous charge pump current. If the
charge pump current is set to its lowest value (LOI = 0) and the
fast acquire circuit is enabled, the instantaneous charge pump
current will never fall below 2 I0 when the pulsewidth is less than
T. Thus, the charge pump current when fast acquire is enabled
is given by:(4)
The recommended setting for LOFA is LOR/16. Choosing a larger
value for LOFA will increase T. Thus, for a given phase differ-
ence between the LO input and the fREF input, the instantaneous
charge pump current will be less than that available for a LOFA
value of LOR/16. Similarly, a smaller value for LOFA will decrease
T, making more current available for the same phase difference.
In other words, a smaller value of LOFA will enable the synthe-
sizer to settle faster in response to a frequency hop than will a
large LOFA value. Care must be taken to choose a value for
LOFA that is large enough (values greater than 4 recommended)
to prevent the loop from oscillating back and forth in response
to a frequency hop.
Table VII.SPI Registers Associated with LO Synthesizer
AD9874The bias, IBIAS, of the negative-resistance core has four pro-
grammable settings. Lower equivalent Q of the LC tank circuit
may require a higher bias setting of the negative-resistance core
to ensure proper oscillation. RBIAS should be selected so the
common-mode voltage at CLKP and CLKN is approximately
1.6 V. The synthesizer may be disabled via the CK standby bit
to allow the user to employ an external synthesizer and/or VCO
in place of those resident on the IC. Note, if an external CLK
source or VCO is used, the clock oscillator must be disabled via
the CKO standby bit.
The phase noise performance of the clock synthesizer is depen-
dent on several factors, including the CLK oscillator IBIAS
setting, the charge pump setting, the loop filter component
values, and the internal fREF setting. Figures 7b and 7c show
how the measured phase noise attributed to the clock synthe-
sizer varies (relative to an external fCLK) as a function of the
IBIAS setting and charge pump setting for a –31 dBm IFIN signal
at 73.35 MHz with an external LO signal at 71.1 MHz. Figure
7b shows that the optimum phase noise is achieved with the
highest IBIAS (CKO) setting, while Figure 7c shows that the
higher charge pump values provide the optimum performance
for the given loop filter configuration. The AD9874 clock syn-
thesizer and oscillator were set up to provide a fCLK of 18 MHz
from an external fREF of 16.8 MHz. The following external
component values were selected for the synthesizer: RF= 390 Ω,
RD = 2 kΩ, CZ = 0.68 µF, CP = 0.1 µF, COSC = 91pF, LOSC =
1.2µH, and CVAR = Toshiba 1SV228 Varactor.
Figure 7b. CLK Phase Noise vs. IBIAS Setting (CKO)
(CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60
with fREF = 100kHz)
CLOCK SYNTHESIZERThe clock synthesizer is a fully programmable integer-N PLL
capable of 2.2kHz resolution at clock input frequencies up toMHz and reference frequencies up to 25MHz. It is similar
to the LO synthesizer described previously in Figure 4 with the
following exceptions:It does not include an 8/9 prescaler nor an A counter.It includes a negative-resistance core that when used in conjunc-
tion with an external LC tank and varactor, serves as the VCO.
The 14-bit reference counter and 13-bit N-divider counter can
be programmed via the following registers: CKR and CKN.
The clock frequency, fCLK, is related to the reference
frequency by the following equation:(5)
The charge pump current is programmable via the CKI register(6)
The fast acquire subcircuit of the charge pump is controlled by
the CKFA Register in the same manner as the LO synthesizer is
controlled by the LOFA Register. An on-chip lock detect function
(enabled by the CKF bit) automatically increases the output
current for faster settling during channel changes. The synthe-
sizer may also be disabled using the CK standby bit located in
the STBY Register.
Figure 7a.External Loop Filter, Varactor, and LC Tank
Are Required to Realize a Complete Clock Synthesizer
The AD9874 clock synthesizer circuitry includes a negative-
resistance core so that only an external LC tank circuit with a
varactor is needed to realize a voltage controlled clock oscillator
(VCO). Figure 7a shows the external components required to
complete the clock synthesizer along with the equivalent input
circuitry of the CLK input. The resonant frequency of the VCO
is approximately determined by LOSC and the series equivalent
capacitance of COSC and CVAR. As a result, LOSC, COSC, and
CVAR should be selected to provide a sufficient tuning range to
ensure proper locking of the clock synthesizer.
