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AD9857AST
CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
REV.0
CMOS 200 MSPS 14-Bit
Quadrature Digital Upconverter
FEATURES
200 MHz Internal Clock Rate
14-Bit Data Path
Excellent Dynamic Performance
80 dB SFDR @ 65 MHz (�100 kHz) AOUT
4�–20� Programmable Reference Clock Multiplier
Reference Clock Multiplier PLL Lock Detect Indicator
Internal 32-Bit Quadrature DDS
FSK Capability
8-Bit Output Amplitude Control
Single-Pin Power-Down Function
Four Programmable, Pin-Selectable Signal “Profiles”
SIN(x)/x Correction (Inverse SINC Function)
Simplified Control Interface
10 MHz Serial, 2- or 3-Wire SPI-Compatible
3.3 V Single Supply
Single-Ended or Differential Input Reference Clock
80-Lead LQFP Surface-Mount Packaging
Three Modes of Operation
Quadrature Modulator Mode
Single-Tone Mode
Interpolating DAC Mode
APPLICATIONS
HFC Data, Telephony, and Video Modems
Wireless Base Station
Agile, L.O. Frequency Synthesis
Broadband Communications
GENERAL DESCRIPTIONThe AD9857 integrates a high-speed direct-digital synthesizer
(DDS), a high-performance, high-speed 14-bit digital-to-analog
converter (DAC), clock multiplier circuitry, digital filters, and other
DSP functions onto a single chip, to form a complete quadrature
digital upconverter device. The AD9857 is intended to function as
a universal I/Q modulator and agile upconverter, single-tone DDS,
or interpolating DAC for communications applications, where
cost, size, power dissipation, and dynamic performance are critical
attributes.
The AD9857 offers enhanced performance over the industry-
standard AD9856, as well as providing additional features.
The AD9857 is available in a space-saving surface-mount
package and is specified to operate over the extended industrial
temperature range of –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9857–SPECIFICATIONS
(VS = 3.3 V � 5%, RSET = 1.96 k�, External reference clock frequency = 10 MHz
with REFCLK Multiplier enabled at 20�).MODULATOR CHARACTERISTICS (65 MHz AOUT)
INVERSE SINC FILTER (Variation in Gain from
AD9857TIMING CHARACTERISTICS
CMOS LOGIC INPUTS
NOTESWake-Up Time refers to recovery from Full Sleep Mode. The longest time required is for the Reference Clock Multiplier PLL to lock up (if it is being used). The
Wake-Up Time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the Reference Clock Multi-
plier lock can be determined by observing the signal on the PLL_LOCK pin.SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the Reference Clock Multiplier is used to multiply the external reference frequency, the
SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor. If the Reference Clock Multiplier is not
used, the SYSCLK frequency is the same as the external REFCLK frequency.CIC = 2, INV SINC ON, FTW = 40%, PLL OFF, Auto Power-Down Between Burst On, TxENABLE Duty Cycle = 25%.
Specifications subject to change without notice.
AD9857
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9857 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Maximum Junction Temperature . . . . . . . . . . . . . . . . .150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.7 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .5 mA
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . .300°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
Test Level–100% Production Tested.
III–Sample Tested Only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing for
industrial operating temperature range.
PIN CONFIGURATION
DIFFCLKEN
AGND
AVDD
AGND
PLL_FILTER
AVDD
AGND
DAC_RSET
DAC_BP
AVDD
AGND
IOUT
IOUT
AGND
AVDD
AGND
D13
D12
D11
D10
DVDD
DVDD
DVDD
DGND
DGND
DGND
TxENABLEPDCLK/FUDDGNDDGNDDGNDDVDDDVDDDVDDDGNDDGNDDGNDCIC_OVRFLPLL_LOCKRESETDPDAGNDAVDDREFCLKREFCLKAGND
PIN FUNCTION DESCRIPTIONS34, 41, 51, 52, 57
35, 37, 38, 43, 48,
54, 58, 64
36, 39, 40, 42, 44, 47,
53, 56, 59, 61, 65
AD9857
Typical Modulated Output Spectral PlotsFigure 1.QPSK at 42 MHz and 5.12 MS/s; 10.24 MHz
External Clock with REFCLK Multiplier = 12, CIC Interpolation
Rate = 3, 4� Oversampled Data
Figure 2.64-QAM at 28 MHz and 6 MS/s; 36 MHz External
Clock with REFCLK Multiplier = 4, CIC Interpolation Rate =
2, 3� Oversampled Data
Figure 3.16-QAM at 65 MHz and 2.56 MS/s; 10.24 MHz
External Clock with REFCLK Multiplier = 18, CIC Interpolation
Rate = 9, 4� Oversampled Data
START 0Hz5MHz/STOP 50MHz
–80Figure 4.256-QAM at 38 MHz and 6 MS/s; 48 MHz External
Clock with REFCLK Multiplier = 4, CIC Interpolation Rate =
2, 4� Oversampled Data
Typical Single-Tone Output Spectral PlotsFigure 5.21 MHz Single-Tone Output
Figure 6.65 MHz Single-Tone Output
Figure 7.42 MHz Single-Tone Output
Figure 8.79 MHz Single-Tone Output
AD9857
Typical Narrowband SFDR Spectral PlotsFigure 9.70.1 MHz Narrowband SFDR, 10 MHz External
Clock with REFCLK Multiplier = 203
Figure 10.70.1 MHz Narrowband SFDR, 200 MHz External
Clock with REFCLK Multiplier Disabled
Typical Plots of Output ConstellationsFigure 11. QPSK, 65 MHz, 2.56 MS/s
Figure 12. 64-QAM, 42 MHz, 6 MS/s
Figure 13. GMSK Modulation, 13 MS/s
Figure 14. 16-QAM, 65 MHz, 2.56 MS/s
Figure 15. 256-QAM, 42 MHz, 6 MS/s
AD9857
MODES OF OPERATIONThe AD9857 has three operating modes:Quadrature Modulation Mode (Default)Single-Tone ModeInterpolating DAC Mode
Mode selection is accomplished by programming a control reg-
ister via the Serial Port. The Inverse SINC filter and output scale
multiplier are available in all three modes.
Quadrature Modulation ModeIn Quadrature Modulation Mode both the I and Q data paths
are active. A block diagram of the AD9857 operating in the
Quadrature Modulation Mode is shown in Figure 16.
In Quadrature Modulation Mode, the PDCLK/FUD pin is an
output and functions as the Parallel Data Clock (PDCLK), which
serves to synchronize the input of data to the AD9857. In this
mode, the input data must be synchronized with the rising edge
of PDCLK. The PDCLK operates at twice the rate of either the
I or Q data path. This is because of the fact that the I and Q data
must be presented to the parallel port as two 14-bit words mul-
tiplexed in time. One I word and one Q word together comprise
one internal sample. Each sample is propagated along the inter-
nal data pathway in parallel fashion.
The DDS Core provides a quadrature (sin and cos) local oscilla-
tor signal to the quadrature modulator, where the I and Q data
are multiplied by the respective phase of the carrier and summed
together, to produce a quadrature-modulated data stream.
All of this occurs in the digital domain, and only then is the digital
data stream applied to the 14-bit DAC to become the quadrature-
modulated analog output signal.
Figure 16.Quadrature Modulation Mode
Single-Tone ModeA block diagram of the AD9857 operating in the Single-Tone
Mode is shown in Figure 17. In the Single-Tone Mode both the
I and Q data paths are disabled from the 14-bit Parallel Data
Port up to and including the modulator. The PDCLK/FUD
pin is an input and functions as a Frequency Update (FUD)
control signal. This is necessary because the frequency tuning
word is programmed via the asynchronous serial port. The FUD
signal causes the new frequency tuning word to become active.
In Single-Tone Mode, the cosine portion of the DDS serves as
the signal source. The output signal consists of a single frequency
as determined by the tuning word stored in the appropriate control
register, per each profile.
In the Single-Tone Mode, no 14-bit parallel data is applied to the
AD9857. The internal DDS core is used to produce a single fre-
quency signal according to the tuning word. The single-tone signal
then moves toward the output, where the Inverse SINC filter and
the output scaling can be applied. Finally, the digital single-tone
signal is converted to the analog domain by the 14-bit DAC.
Figure 17.Single-Tone Mode
AD9857
Interpolating DAC ModeA block diagram of the AD9857 operating in the Interpolating
DAC Mode is shown in Figure 18. In this mode the DDS and
modulator are both disabled and only the I data path is active.
The Q data path is disabled from the 14-bit Parallel Data Port
up to and including the modulator.
As with the Quadrature Modulation Mode, the PDCLK pin is
an output and functions as a clock which serves to synchronize
the input of data to the AD9857. Unlike the Quadrature Modu-
lation Mode, however, the PDCLK operates at the rate of the I
data path. This is because only I data is being presented to the
parallel port as opposed to the interleaved I/Q format of the
Quadrature Modulation Mode.
In the Interpolating DAC Mode, the baseband data supplied at the
parallel port remains at baseband at the output; i.e., no modulation
takes place. However, a sample rate conversion takes place based
on the programmed interpolation rate. The interpolation hardware
performs the necessary signal processing required to eliminate the
aliased images at baseband that would otherwise result from a
sample rate conversion. The interpolating DAC function is effec-
tively an oversampling operation with the original input spectrum
intact but sampled at a higher rate.
Signal Processing PathTo better understand the operation of the AD9857 it is helpful to
follow the signal path from input, through the device, to the
output, examining the function of each block (refer to the Func-
tional Block Diagram). The input to the AD9857 is a 14-bit
parallel data path. This assumes that the user is supplying the
data as interleaved I and Q values. Any encoding, interpolation,
The AD9857 demultiplexes the interleaved I and Q data into two
separate data paths inside the part. This means that the input
sample rate (fDATA), the rate at which 14-bit words are presented to
the AD9857, must be 2× the internal I/Q Sample Rate (fIQ),
the rate at which the I/Q pairs are processed. In other words,
fDATA = 2 × fIQ.
From the input demultiplexer to the Quadrature Modulator, the
data path of the AD9857 is a dual I/Q path.
All timing within the AD9857 is provided by the internal System
Clock (SYSCLK) signal. The externally provided Reference
Clock signal may be used as is (1×), or multiplied by the internal
Clock Multiplier (4×–20×) to generate the SYSCLK. All other
internal clocks and timing are derived from the SYSCLK.
Input Data AssemblerIn the Quadrature Modulation or Interpolating DAC Modes the
device accepts 14-bit, two’s complement data at its parallel data
port. The timing of the data supplied to the parallel port may
be easily facilitated with the PDCLK/FUD pin of the AD9857,
which is an output in the Quadrature Modulation Mode and the
Interpolating DAC mode. In the Single-Tone Mode, the same
pin becomes an input to the device and serves as a FREQUENCY
UPDATE (FUD) strobe.
Frequency control words are programmed into the AD9857 via
the serial port (see the Control Register Description). Since the
serial port is an asynchronous interface, when programming new
frequency tuning words into the on-chip profile registers, the
AD9857’s internal frequency synthesizer must be synchronized
with external events. The purpose of the FUD input pin is to
synchronize the start of the frequency synthesizer to the external
Figure 18.Interpolating DAC Mode
Figure 19.14-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode
Figure 20.14-Bit Parallel Port Timing Diagram—Interpolating DAC Mode
(see the Profile section) to be transferred to the accumulator of
the DDS, thus starting the frequency synthesis process.
After loading the frequency tuning word to a profile, a FUD signal
is not needed when switching between profiles using the two profile
select pins (PS0, PS1). When switching between profiles, the fre-
quency tuning word in the profile register is becomes effective.
In the Quadrature Modulation mode the PDCLK rate is twice
the rate of the I (or Q) data rate. The AD9857 expects interleaved
I and Q data words at the parallel port with one word per PDCLK
rising edge. One I word and one Q word together comprise one
internal sample. Each sample is propagated along the internal
data pathway in parallel.
In the Interpolating DAC mode, however, the PDCLK rate is
the same as the “I” data rate since the “Q” data path is inactive.
In this mode, each PDCLK rising edge latches a data word into
the “I” data path.
The PDCLK is provided as a continuous clock (i.e., always
active). However, the assertion of PDCLK may be optionally
qualified internally by the PLL Lock Indicator if the user elects to
set the PLL Lock Control bit in the appropriate Control Register.
Data supplied by the user to the 14-bit Parallel Port is latched
into the device coincident with the rising edge of the PDCLK.
In the Quadrature Modulation Mode the rising edge of the
TxENABLE signal is used to synchronize the device. While
TxENABLE is in the Logic 0 state, the device ignores the 14-bit
data applied to the parallel port and allows the internal data path to
be flushed by forcing 0s down the I and Q data pathway. On the
rising edge of TxENABLE the device is ready for the first “I”
word. The first “I” word is latched into the device coincident with
the rising edge of PDCLK. The next rising edge of PDCLK
latches in a “Q” word, etc., until TxENABLE is set to a Logic 0
state by the user.
When in the Quadrature Modulation Mode it is important that
the user ensure that an even number of PDCLK intervals are
observed during any given TxENABLE period. This is because
the device must capture both an I and a Q value before the data
can be processed along the internal data pathway.
The timing relationship between TxENABLE, PDCLK, and
DATA is shown in Figures 19 and 20.
AD9857
Fixed Interpolator (4�)This block is a fixed 4× interpolator. It is implemented as two
half-band filters. The output of this stage is the original data
upsampled by 4×.
Before presenting a detailed description of the half-band filters,
recall that in the case of the Quadrature Modulation Mode the
input data stream is representative of complex data; i.e., two
input samples are required to produce one I/Q data pair. The
I/Q sample rate is one-half the input data rate. The I/Q sample
rate (the rate at which I or Q samples are presented to the input
of the first half-band filter) will be referred to as fIQ. Since the
AD9857 is a quadrature modulator, fIQ represents the baseband
of the internal I/Q sample pairs. It should be emphasized here
that fIQ is not the same as the baseband of the user’s symbol rate
data, which must be upsampled before presentation to the AD9857
(as will be explained later). The I/Q sample rate (fIQ) puts a
limit on the minimum bandwidth necessary to transmit the fIQ
spectrum. This is the familiar Nyquist limit and is equal to one-half
fIQ, hereafter referred to as fNYQ.
Together, the two half-band filters provide a factor-of-four increase
in the sampling rate (4 × fIQ or 8 × fNYQ). Their combined insertion
loss is 0.01 dB, so virtually no loss of signal level occurs through
the two half-band filters. Both half-band filters are linear phase fil-
ters, so that virtually no phase distortion is introduced within the
pass band of the filters. This is an important feature as phase
distortion is generally intolerable in a data transmission system.
The half-band filters are designed so that their composite perfor-
mance yields a usable pass band of 80% of the baseband Nyquist
frequency (0.2 on the frequency scale below). Within that pass
band the ripple will not exceed 0.002 dB. The stopband extends
from 120% to 400% of the baseband Nyquist frequency (0.3
to 1.0 on the frequency scale below) and offers a minimum of
85 dB attenuation. The composite response of the two half-
band filters together are shown in Figures 22 and 23.
FREQUENCY0.20.4
SAMPLE RATEFigure 22.Half-Band 1 and 2 Frequency Response;
Frequency Relative to HB1 Output Sample Rate
Inverse CIC FilterThe Inverse CIC Filter precompensates the data in order to off-
set the slight attenuation gradient imposed by the CIC filter (see
the Programmable (2×–63×) CIC Interpolating Filter section).
The I (or Q) data entering the first half-band filter occupies a
maximum bandwidth of one-half fDATA as defined by Nyquist
(where fDATA is the sample rate at the input of the first half-band
filter). This is shown graphically in Figure 21.
Figure 21.CIC Filter Response
Table I.Parallel Data Bus TimingIf the CIC filter is employed, the inband attenuation gradient
could pose a problem for those applications requiring an extremely
flat pass band. For example, if the spectrum of the data as supplied
to the AD9857 I or Q path occupies a significant portion of the
one-half fDATA region, the higher frequencies of the data spectrum
will receive slightly more attenuation than the lower frequencies
(the worst-case overall droop from f = 0 to one-half fDATA is
< 0.8 dB). This may not be acceptable in certain applications. The
Inverse CIC filter has a response characteristic that is the inverse of
the CIC filter response over the one-half fDATA region.
The net result is that the product of the two responses yields in
an extremely flat pass band, thereby eliminating the inband
attenuation gradient introduced by the CIC filter. The price to
be paid is a slight attenuation of the input signal of approximately
0.5 dB for a CIC interpolation rate of 2 dB and 0.8 dB for inter-
polation rates of 3 to 63.
The Inverse CIC Filter is implemented as a digital FIR filter
with a response characteristic that is the inverse of the Program-
mable CIC Interpolator. The product of the two responses yields a
nearly flat response over the baseband Nyquist bandwidth. The
Inverse CIC filter provides frequency compensation that yields a
response flatness of ±0.05 dB over the baseband Nyquist band-
width, allowing the AD9857 to provide excellent SNR over its
performance range.
The Inverse CIC Filter can be bypassed by setting Control
Register 06h<0>. It is automatically bypassed if the CIC
0.050.100.150.200.25 –0.002
FREQUENCY
SAMPLE RATEFigure 23.Half-Band 1 and 2 Pass Band Detail; Frequency
Relative to HB1 Output Sample Rate
The usable bandwidth of the filter chain puts a limit on the
maximum data rate that can be propagated through the AD9857.
A look at the pass band detail of the half-band filter response
indicates that in order to maintain an amplitude error of no
more than 1 dB, we are restricted to signals having a bandwidth
of no more than about 90% of fNYQ. Thus, in order to keep the
bandwidth of the data in the flat portion of the filter pass band,
the user must oversample the baseband data by at least a factor
of two prior to presenting it to the AD9857. Note that without
oversampling, the Nyquist bandwidth of the baseband data cor-
responds to the fNYQ. Because of this, the upper end of the data
bandwidth will suffer 6 dB or more of attenuation due to the
frequency response of the half-band filters. Furthermore, if the
baseband data applied to the AD9857 has been pulse shaped
there is an additional concern.
Typically, pulse shaping is applied to the baseband data via a
filter having a raised cosine response. In such cases, an α value
is used to modify the bandwidth of the data where the value of α
is such that 0 < α < 1. A value of 0 causes the data bandwidth
to correspond to the Nyquist bandwidth. A value of 1 causes the
data bandwidth to be extended to twice the Nyquist bandwidth.
Thus, with 2× oversampling of the baseband data and α = 1, the
Nyquist bandwidth of the data will correspond with the I/Q
Nyquist bandwidth. As stated earlier, this results in problems
near the upper edge of the data bandwidth due to the roll-off
attenuation of the half-band filters. The following diagrams
illustrate the relationship between α and the bandwidth of raised
cosine shaped pulses. The problem area is indicated by the shading
in the tail of the pulse with α = 1, which extends into the roll-off
region of the half-band filter.
The effect of raised cosine filtering on baseband pulse bandwidth,
and the relationship to the half-band filter response is shown in
Figure 24.
Figure 24.Effect of Alpha
Programmable (2�–63�) CIC Interpolating FilterThe Programmable Interpolator is implemented as a CIC
(Cascaded Integrator-Comb) filter. It is programmable by a
6-bit control word, giving a range of 2× to 63× interpolation.
This interpolator has a low-pass frequency characteristic that is
compensated by the Inverse CIC filter.
The Programmable Interpolator can be bypassed to yield a 1× (no
interpolation) configuration by setting the bit in the appropri-
ate control register, per each profile. Whenever the Programmable
Interpolator is bypassed (1× CIC rate) power to the stage is
removed. If the Programmable Interpolator is bypassed, the
Inverse CIC filter (see above) is automatically bypassed, since
its compensation is not needed in this case.
The output of the Programmable Interpolator is the data from
the 4× interpolator upsampled by an additional 2× to 63×, accord-
ing to the rate chosen by the user. This results in the input data
being upsampled by a factor of 8× to 252×.
AD9857The transfer function of the CIC Interpolating Filter is:
where R is the interpolation rate, and f is the frequency relative
to SYSCLK.
Quadrature ModulatorThe digital quadrature modulator stage is used to frequency shift
the baseband spectrum of the incoming data stream up to the
desired carrier frequency (this process is known as upconversion).
It should be noted that at this point the incoming data has been
converted from an incoming sampling rate of fIN to an I/Q sam-
pling rate equal to SYSCLK. The purpose of the upsampling
process is to make the data sampling rate equal to the sampling
rate of the carrier signal.
The carrier frequency is controlled numerically by a Direct Digital
Synthesizer (DDS). The DDS uses the internal reference clock
(SYSCLK) to generate the desired carrier frequency with a high
degree of precision. The carrier is applied to the I and Q multi-
pliers in quadrature fashion (90° phase offset) and summed to yield
a data stream that represents the quadrature modulated carrier.
A key point is that the modulation is done digitally which elimi-
nates the phase and gain imbalance and crosstalk issues typically
associated with analog modulators. Note that the modulated
“signal” is actually a number stream sampled at the rate of
SYSCLK, the same rate at which the output D/A converter is
clocked.
The quadrature modulator operation is also controlled by spectral
invert bits in each of the four profiles. The quadrature modu-
lation takes the form:
I × COS(ω) + Q × SIN(ω) when the spectral invert bit is set to a
Logic 1.
I × COS(ω) – Q × SIN(ω) when the spectral invert bit is set
to a Logic 0.
DDS CoreThe direct digital synthesizer (DDS) block generates the sin/cos
carrier reference signals that digitally modulate the I/Q data
paths. The DDS frequency is tuned via the serial control port
with a 32-bit tuning word (per profile). This allows the AD9857’s
output carrier frequency to be very precisely tuned while still
providing output frequency agility.
The equation relating output frequency (fOUT) of the AD9857
digital modulator to the frequency tuning word (FTWORD)
and the system clock (SYSCLK) is:
fOUT = (FTWORD × SYSCLK)/232
where fOUT and SYSCLK frequencies are in Hz and FTWORD is
a decimal number from 0 to 2,147,483,647 (231–1)
Example: Find the FTWORD for fOUT = 41 MHz and SYSCLK =
122.88 MHz
If fOUT = 41 MHz and SYSCLK = 122.88 MHz, then
FTWORD = 556AAAAB hex
Loading 556AAAABh into control bus registers 08h–0Bh (for
Inverse SINC FilterThe sampled carrier data stream is the input to the digital-to-
analog converter (DAC) integrated onto the AD9857. The DAC
output spectrum is shaped by the characteristic sin(x)/x (or
SINC) envelope, due to the intrinsic zero-order hold effect asso-
ciated with DAC-generated signals. Since the shape of the SINC
envelope is well known, it can be compensated for. This envelope
restoration function is provided by the optional inverse SINC
filter preceding the DAC. This function is implemented as an
FIR filter, which has a transfer function that is the exact inverse of
the SINC response. When the Inverse SINC Filter is selected, it
modifies the incoming data stream so that the desired carrier
envelope, which would otherwise be shaped by the SINC envelope,
is restored. It should be noted, however, that this correction is
only complete for carrier frequencies up to approximately 45%
of SYSCLK.
It should be noted that the inverse SINC filter introduces about a
3.5 dB loss at low frequencies as compared to the gain with the
inverse SINC filter turned off. This is done to flatten the overall
gain from dc to 45% of SYSCLK.
The inverse SINC filter can be bypassed if it is not needed. If the
inverse SINC filter is bypassed, its clock is stopped, thus reducing
the power dissipation of the part.
Output Scale MultiplierAn 8-bit multiplier (Output Scale Value in the block diagram) pre-
ceding the DAC provides the user with a means of adjusting the
final output level. The multiplier value is programmed via the
appropriate control registers, per each profile. The LSB weight
is 2–7, which yields a multiplier range of 0 to 1.9921875, or
nearly 2×. Since the quadrature modulator has an intrinsic loss
of 3 dB (1/√2), programming the multiplier for a value of
√2) will restore the data to the full-scale range of the DAC when
the device is operating in the Quadrature Modulation Mode. Since
the AD9857 defaults to the Modulation Mode, the default value
for the multiplier is B5h (which corresponds to √2).
Programming the output scale multiplier to unity gain (80h) by-
passes the stage, reducing power dissipation.
14-Bit D/A ConverterA 14-bit digital-to-analog converter (DAC) is used to convert the
digitally processed waveform into an analog signal. The worst-case
spurious signals due to the DAC are the harmonics of the funda-
mental signal and their aliases (please see Analog Devices, DDS
Tutorial at http:///dds for a detailed explanation
of aliases). The wideband 14-bit DAC in the AD9857 maintains
spurious-free dynamic range (SFDR) performance of –60 dBc
up to AOUT = 42 MHz and –55 dBc up to AOUT = 65 MHz.
The conversion process will produce aliased components of the
fundamental signal at n � SYSCLK ± FCARRIER (n = 1, 2, 3).
These are typically filtered with an external RLC filter at the DAC
output. It is important for this analog filter to have a sufficiently
flat gain and linear phase response across the bandwidth of
interest to avoid modulation impairments.
