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AD9856AST
CMOS 200 MHz Quadrature Digital Upconverter
REV.B
CMOS 200 MHz
Quadrature Digital Upconverter
FUNCTIONAL BLOCK DIAGRAM12
COSINESINE
COMPLEX
DATA IN
REFERENCE
CLOCK IN
TxENABLE
(I/Q SYNC)
PROFILE
SELECT
PROFILE
SELECT
MASTER
RESET
SPI INTERFACE
TO AD8320/AD8321
PROGRAMMABLE
CABLE DRIVER
AMPLIFIER
DAC
RSET
DC-80 MHz
OUTPUT
BIDIRECTIONAL SPI CONTROL INTERFACE:
32-BIT FREQUENCY TUNING WORD
FREQUENCY UPDATE
INTERPOLATION FILTER RATE
REFERENCE CLOCK MULTIPLIER RATE
SPECTRAL PHASE INVERSION ENABLE
CABLE DRIVER AMPLIFIER CONTROL1212
AD9856
FEATURES
Universal Low Cost Modulator Solution for
Communications Applications
DC to 80 MHz Output Bandwidth
Integrated 12-Bit D/A Converter
Programmable Sample Rate Interpolation Filter
Programmable Reference Clock Multiplier
Internal SIN(x)/x Compensation Filter
>52 dB SFDR @ 40 MHz AOUT
>48 dB SFDR @ 70 MHz AOUT
>80 dB Narrowband SFDR @ 70 MHz AOUT
+3 V Single Supply Operation
Space-Saving Surface-Mount Packaging
Bidirectional Control Bus Interface
Supports Burst and Continuous Tx Modes
Single Tone Mode for Frequency Synthesis Applications
Four Programmable, Pin-Selectable Modulator Profiles
Direct Interface to AD8320/AD8321 PGA Cable Driver
GENERAL DESCRIPTIONThe AD9856 integrates a high speed direct-digital synthesizer
(DDS), a high performance, high speed 12-bit digital-to-analog
converter (DAC), clock multiplier circuitry, digital filters and
other DSP functions onto a single chip, to form a complete
quadrature digital upconverter device. The AD9856 is intended
to function as a universal I/Q modulator and agile upconverter
for communications applications, where cost, size, power dissi-
pation and dynamic performance are critical attributes.
The AD9856 is available in a space-saving surface mount pack-
age and specified to operate over the extended industrial tem-
perature range of –40°C to +85°C.
APPLICATIONS
HFC Data, Telephony and Video Modems
Wireless and Satellite Communications
Cellular Basestations
AD9856–SPECIFICATIONS
(VS = +3 V 6 5%, RSET = 3.9 kV, External reference clock frequency = 10 MHz
with REFCLK Multiplier enabled at 203).CMOS LOGIC INPUTS
AD9856POWER SUPPLY
NOTESFor 200 MHz operation in Modulation Mode at +85°C operating temperature, VS must be +3 V min.Assuming 1.3 kW and 0.01 mF loop filter components.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*Maximum Junction Temperature . . . . . . . . . . . . . . . .+165°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4 V
Operating Temperature . . . . . . . . . . . . . . . . .–40°C to +85°C
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . .–0.7 V to +VS
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . .+300°C
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . .5 mAJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . .38°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9856 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
EXPLANATION OF TEST LEVELS
Test Level–100% Production Tested.
III–Sample Tested Only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–Devices are 100% production tested at +25°C and
guaranteed by design and characterization testing for
industrial operating temperature range.
AD9856
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
CA DATA
CA ENABLE
PLL SUPPLY
PLL FILTER
PLL GND
AGND
IOUT
TxENABLE
D11
D10
DVDD
DGND
NC = NO CONNECT
DVDD
DGND
IOUTB
AGND
AVDD
DAC REF BYPASS
BG REFBYPASSDAC RSET
DVDD
DGNDD1D2D3D4
AGND
SYNC I/O
REFCLKSCLKRESETPS0DVDDDGNDCA CLKPS1
SDO
SDIO*In most cases optimal performance is achieved with no external connection. For extremely noisy environments BG REF BYPASS can be bypassed with up to a
0.1 mF capacitor to AGND (Pin 23). DAC REF BYPASS can be bypassed with up to a 0.1 mF capacitor to AVDD (Pin 27).
FUNCTIONAL BLOCK AND MODE DESCRIPTIONInternal Reference Clock Multiplier
Profile Select
Interpolating Range
AD9856
Typical Modulated Output Spectral Plots
START 0Hz 5MHz/ STOP 50MHz
REF LVL
–25dBm
dBm
1AP
RBW10kHzRF ATT10dB
VBW1kHz
SWT12.5s UnitdBmFigure 1.QPSK at 42 MHz and 2.56 MS/s; 10.24 MHz
External Clock with REFCLK Multiplier = 12, CIC = 3,
HB3 On, 2· Data
START 0Hz 4MHz/ STOP 40MHz
REF LVL
–30dBm
dBm
1AP
RBW 10kHzRF ATT10dB
VBW 1kHz
SWT10sUNITdBmFigure 2.64-QAM at 28 MHz and 6 MS/s; 36 MHz External
Clock with REFCLK Multiplier = 4, CIC = 2, HB3 Off, 3· Data
Figure 3.16-QAM at 65 MHz and 2.56 MS/s; 10.24 MHz
External Clock with REFCLK Multiplier = 18, CIC = 9,
HB3 Off, 2· Data
Figure 4.256-QAM at 38 MHz and 6 MS/s; 48 MHz External
Clock with REFCLK Multiplier = 4, CIC = 2, HB3 Off, 4· Data
Typical Single Tone Output Spectral Plots
START 0Hz 10MHz/ STOP 100MHz
REF LVL
–5dBm
dBm
1AP
RBW3kHzRF ATT20dB
VBW 3kHz
SWT28sUNIT dBFigure 5.21 MHz CW Output
START 0Hz 10MHz/ STOP 100MHz
REF LVL
–5dBm
dBm
1AP
RBW3kHzRF ATT20dB
VBW 3kHz
SWT28sUNIT dBFigure 6.65 MHz CW Output
Figure 7.42 MHz CW Output
Figure 8.79 MHz CW Output
AD9856
Typical Narrowband SFDR Spectral Plots
Typical Phase Noise Spectral Plots
CENTER 70.1MHz 10kHz/ SPAN 100kHz
REF LVL
–5dBm
dBm
1AP
RBW100HzRF ATT20dB
VBW 100Hz
SWT50sUNIT dBFigure 9.70.1 MHz Narrowband SFDR, 10 MHz External
Clock with REFCLK Multiplier = 20·
CENTER 70.1MHz 10kHz/ SPAN 100kHz
REF LVL
–5dBm
dBm
1AP
RBW100HzRF ATT20dB
VBW 100Hz
SWT50sUNIT dBFigure 11.70.1 MHz Narrowband SFDR, 200 MHz External
Clock with REFCLK Multiplier Disabled
CENTER 40.1MHz 500Hz/ SPAN 5kHz
REF LVL
0dBm
dBm
1AP
RBW30HzRF ATT30dB
VBW 30Hz
SWT28sUNIT dBFigure 10.40.1 MHz Output, 10 MHz External Clock with
REFCLK Multiplier = 20·
CENTER 40.1MHz 500Hz/ SPAN 5kHz
REF LVL
0dBm
dBm
1AP
RBW30HzRF ATT30dB
VBW 30Hz
SWT28sUNIT dBFigure 12.40.1 MHz Output, 200 MHz External Clock with
REFCLK Multiplier Disabled
Typical Plots of Output Constellations
–1.9607843757 1.96078437567
TRACE A: CH 1 QPSK MEAS TIME
CONST
/DIV
–1.5Figure 13.QPSK, 65 MHz, 2.56 MS/s
–1.3071895838 1.30718958378
TRACE A: CH 1 64QAM MEAS TIME
CONST
/DIVFigure 14.64-QAM, 42 MHz, 6 MS/s
Figure 15.16-QAM, 65 MHz, 2.56 MS/s
Figure 16.256-QAM, 42 MHz, 6 MS/s
–1.9607843757 1.96078437567
TRACE A: CH 1 MSK1 MEAS TIME
CONST
/DIV
–1.5Figure 17.GMSK Modulation, 13 MS/s
AD9856
Power Consumption
CLOCK SPEED – MHz
POWER CONSUMPTION – mW
800140160200180Figure 18.Power Consumption vs. Clock Speed; +VS =
+3 V, CIC = 2, +25°C
Figure 19.Power Consumption vs. CIC Rate; +VS =
+3 V, 200 MHz, +25°C
Tx ENABLE DUTY CYCLE
POWER CONSUMPTION – mW
105075100Figure 20.Power Consumption vs. Burst Duty Cycle;
+VS = +3 V, CIC = 2, 200 MHz, +25°C
Table I.Serial Control Bus Register Layout
AD9856
REGISTER BIT DEFINITIONS
Control Bits—Register Address 00h and 01h
SDO Active—Register Address 00h, Bit 7. Active high indicatesserial port uses dedicated in/out lines. Default low configures
serial port as single line I/O.
LSB First—Register Address 00h, Bit 6. Active high indicatesserial port access is LSB to MSB format. Default low indicates
MSB to LSB format.
REFCLK Multiplier—Register Address 00h, Bits 5, 4, 3, 2, 1 formthe reference clock multiplier. Valid entries range from
4–20 (decimal). Straight binary to decimal conversion is imple-
mented. For example, to multiply the reference clock by 19 deci-
mal, Program Register Address 00h, Bits 5–1, as 13h. Default value
is 0A (hex).
RESERVED BIT—Register Address 00h, Bit 0. This bit isreserved. Always set this bit to Logic 1 when writing to this
register.
CIC GAIN—Register Address 01h, Bit 7. The CIC GAIN bitmultiplies the CIC filter output by 2. See the Cascaded Inte-
grated Comb Filter section of this data sheet for more details.
Default value is 0 (inactive).
CONTINUOUS MODE—Register Address 01h, Bit 6 is thecontinuous mode configuration bit. Active high, configures the
AD9856 to accept continuous mode timing on the TxENABLE
input. A low configures the device for burst mode timing. De-
fault value is 0 (burst mode).
FULL SLEEP MODE—Register Address 01h, Bit 5. Activehigh full sleep mode bit. When activated, the AD9856 enters a
full shutdown mode, consuming less than 2 mA, after completing
a shutdown sequence. Default value is 0 (awake).
SINGLE TONE MODE—Register Address 01h, Bit 4. Activehigh configures the AD9856 for single tone applications. The
AD9856 will supply a single frequency output as determined by
the frequency tuning word (FTW) selected by the active profile.
In this mode, the 12 input data pins are ignored but should be
tied high or low. Default value is 0 (inactive).
BYPASS INVERSE SINC FILTER—Register Address 01h,Bit 3. Active high, configures the AD9856 to bypass the SIN(x)/
x compensation filter. Defaults value is 0 (Inverse SINC Filter
Enabled).
BYPASS REFCLK Multiplier—Register Address 01h, Bit 2.Active high, configures the AD9856 to bypass the REFCLK
Multiplier function. When active, effectively causes the REFCLK
Multiplier factor to be 1. Defaults value is 1 (REFCLK Multi-
plier bypassed).
INPUT FORMAT SELECT—Register Address 01h, Bits 1and 0, form the Input Format Mode bits.
10b = 12-bit mode
01b = 6-bit mode
00b = 3-bit mode
Default value is 10b (12-bit mode).
Profile 1 Registers—Active when PROFILE Inputs Are 00b
FREQUENCY TUNING WORD (FTW)—The frequencytuning word for Profile 1 is formed via a concatenation of regis-
ter addresses 05h, 04h, 03h and 02h. Bit 7 of register address
05h is the most significant bit of the Profile 1 frequency tuning
word. Bit 0 of register address 02h is the least significant bit of
the Profile 1 frequency tuning word. The output frequency
equation is given as: fOUT = (FTW · SYSCLK)/232.
INTERPOLATION RATE—Register Address 06h, Bits 7through 2 form the Profile 1 CIC filter interpolation rate value.
Allowed values range from 2 to 63 (decimal).
SPECTRAL INVERSION—Register Address 06h, Bit 1. Ac-tive high, Profile 1 Spectral Inversion bit. When active, inverted
modulation is performed [I · Cos(wt) + Q · Sin(wt)]. Default is
inactive, logic zero, noninverted modulation [I · Cos(wt) – Q ·
Sin(wt)].
BYPASS HALF-BAND FILTER 3—Register Address 06h, Bit0. Active high, causes the AD9856 to bypass the third half-band
filter stage that precedes the CIC interpolation filter. Bypassing
the third half-band filter negates the 2· upsample inherent with
this filter and reduces the overall interpolation rate of the half-
band filter chain from 8· to 4·. Default value is 0 (half-band 3
enabled).
AD8320/AD8321 GAIN CONTROL—Register Address 07h,Bits 7 through 0 form the Profile 1 AD8320/AD8321 gain bits.
The AD9856 dedicates three output pins, which directly in-
terface to the AD8320/AD8321 cable driver amp. This allows
direct control of the cable driver via the AD9856. See the
Programming/Writing the AD8320/AD8321 Cable Driver Gain
Control section of this data sheet for more details. Bit 7 is the
MSB, Bit 0 is the LSB. Default value is 00h.
Profile 2 Registers—Active when PROFILE Inputs Are 01bProfile 2 Register functionality is identical to Profile 1, with the
exception of the register addresses.
Profile 3 Registers—Active when PROFILE Inputs Are 10bProfile 3 Register functionality is identical to Profile 1, with the
exception of the register addresses.
Profile 4 Registers—Active when PROFILE Inputs Are 11bProfile 4 Register functionality is identical to Profile 1, with the
exception of the register addresses.
THEORY OF OPERATIONTo gain a general understanding of the functionality of the
AD9856 it is helpful to refer to Figure 21, which displays a
block diagram of the device architecture. The following is a
general description of the device functionality. Later sections
will detail each of the data path building blocks.
Modulation Mode OperationThe AD9856 accepts 12-bit data words, which are strobed into
the Data Assembler via an internal clock. The input, TxENABLE,
serves as the “valve” which allows data to be accepted or ig-
nored by the Data Assembler. The user has the option to feed
the 12-bit data words to the AD9856 as single 12-bit words,
dual 6-bit words, or quad 3-bit words. This provides the user
with the flexibility to use fewer interface pins, if so desired.
Furthermore, the incoming data is assumed to be complex, in
that alternating 12-bit words are regarded as the inphase (I) and
quadrature (Q) components of a symbol.
The rate at which the 12-bit words are presented to the AD9856
will be referred to as the Input Sample Rate (fIN). It should be
pointed out that fIN is not the same as the baseband data rate
provided by the user. As a matter of fact, it is required that the
user’s baseband data be upsampled by at least a factor of two
(2) before being applied to the AD9856 in order to minimize
the frequency-dependent attenuation associated with the CIC
filter stage (detailed in a later section).
The Data Assembler splits the incoming data word pairs into
separate I/Q data streams. The rate at which the I/Q data word
pairs appear at the output of the Data Assembler will be referred
to as the I/Q Sample Rate (fIQ). Since two 12-bit input data
words are used to construct the individual I and Q data paths, it
should be apparent that the input sample rate is twice the I/Q
sample rate (i.e., fIN = 2 · fIQ).
Once through the Data Assembler, the I/Q data streams are fed
through two half-band filters (half-band filters #1 and #2). The
combination of these two filters results in a factor of four (4)
increase of the sample rate. Thus, at the output of half-band
filter #2, the sample rate is 4 · fIQ. In addition to the sample
rate increase, the half-band filters provide the low-pass filtering
characteristic necessary to suppress the spectral images pro-
duced by the upsampling process. Further upsampling is avail-
able via an optional third half-band filter (half-band filter #3).
When selected, this provides an overall upsampling factor of
eight (8). Thus, if half-band filter #3 is selected, then the sample
rate at its output is 8 · fIQ.
After passing through the half-band filter stages, the I/Q data
streams are fed to a Cascaded Integrator-Comb (CIC) filter.
This filter is configured as an interpolating filter, which allows
further upsampling rates of any integer value between 2 and 63,
inclusive. The CIC filter, like the half-bands, has a built-in low-
pass characteristic. Again, this provides for suppression of the
spectral images produced by the upsampling process.
The digital quadrature modulator stage following the CIC filters
is used to frequency shift the baseband spectrum of the incom-
ing data stream up to the desired carrier frequency (this process
is known as upconversion). The carrier frequency is controlled
numerically by a Direct Digital Synthesizer (DDS). The DDS
uses its internal reference clock (SYSCLK) to generate the
desired carrier frequency with a high degree of precision. The
carrier is applied to the I and Q multipliers in quadrature fash-
ion (90° phase offset) and summed to yield a data stream that
is the modulated carrier. It should be noted at this point that the
incoming data has been converted from an input sample rate
of fIN to an output sample rate of SYSCLK (see the block
diagram).
The sampled carrier is ultimately destined to serve as the input
data to the digital-to-analog converter (DAC) integrated on the
AD9856. The DAC output spectrum is distorted due to the
intrinsic zero-order hold effect associated with DAC-generated
signals. This distortion is deterministic, however, and follows
the familiar SIN(x)/x (or SINC) envelope. Since the SINC
distortion is predictable, it is also correctable. Hence, the presence
of the optional Inverse SINC filter preceding the DAC. This is a
FIR filter, which has a transfer function conforming to the inverse
of the SINC response. Thus, when selected, it modifies the incom-
ing data stream so that the SINC distortion, which would other-
wise appear in the DAC output spectrum is virtually eliminated.
As mentioned earlier, the output data is sampled at the rate of
SYSCLK. Since the AD9856 is designed to operate at SYSCLK
frequencies up to 200 MHz, there is the potential difficulty of
trying to provide a stable input clock (REFCLK). Although
stable, high frequency oscillators are available commercially they
tend to be cost prohibitive. To alleviate this problem, the AD9856
has a built-in programmable clock multiplier circuit. This allows
the user to use a relatively low frequency (thus, less expensive)
oscillator to generate the REFCLK signal. The low frequency
REFCLK signal can then be multiplied in frequency by an
integer factor of between 4 and 20, inclusive, to become the
SYSCLK signal.
AD9856
Single Tone Output OperationThe AD9856 can be configured for frequency synthesis applica-
tions by writing the single tone bit true. In single tone mode, the
AD9856 disengages the modulator and preceding datapath logic
to output a spectrally pure single frequency sine wave. The
AD9856 provides for a 32-bit frequency tuning word, which
results in a tuning resolution of 0.046 Hz at a SYSCLK rate of
200 MHz.
A good rule of thumb when using the AD9856 as a frequency
synthesizer is to limit the fundamental output frequency to 40%
of SYSCLK. This avoids generating aliases too close to the
desired fundamental output frequency, thus minimizing the cost
of filtering the aliases.
All applicable programming features of the AD9856 apply when
configured in single tone mode. These features include:Frequency hopping via the PROFILE inputs and associated
tuning word, which allows Frequency Shift Keying (FSK)
modulation.Ability to bypass the REFCLK Multiplier, which results in
lower phase noise and reduced output jitter.Ability to bypass the SIN(x)/x compensation filter.Full power-down mode.
INPUT WORD RATE (fW) vs. REFCLK RELATIONSHIPThere is a fundamental relationship between the input word rate
(fW) and the frequency of the clock that serves as the timing
source for the AD9856 (REFCLK). fW is defined as the rate at
which K-bit data words (K = 3, 6 or 12) are presented to the
AD9856. There are, however, a number of factors that affect
this relationship. They are:The interpolation rate of the CIC filter stage.Whether or not Half-Band Filter #3 is bypassed.The value of REFCLK Multiplier (if selected).Input Word Length.
This relationship can be summed up with the following equation:
REFCLK = (2 HNfW)/MI
Where H, N, I and M are integers and are determined as follows:=| 1:Half-Band Filter #3 Bypassed
| 2:Half-Band Filter #3 Enabled=| 1:REFCLK Multiplier Bypassed
| 4 £ M £ 20:REFCLK Multiplier Enabled=| 1:Full Word Input Format
| 2:Half Word Input Format
| 4:Quarter Word Input Format=CIC interpolation rate (2 £ N £ 63)
It should be obvious from these conditions that REFCLK and
fW have an integer ratio relationship. It is of utmost importance
that the user chooses a value of REFCLK, which will ensure
that this integer ratio relationship is maintained.
I/Q DATA SYNCHRONIZATIONAs mentioned above, the AD9856 accepts I/Q data pairs, twos
form a 12-bit word. The quarter word mode accepts multiple
3-bit I and Q data inputs to form a 12-bit word. For all word
length modes, the AD9856 assembles the data for signal pro-
cessing into time aligned, parallel 12-bit I/Q pairs. In addition to
the word length flexibility, the AD9856 operates in two “input
timing” modes, burst or continuous, programmable via the
serial port.
For burst mode input timing, no external data clock needs to be
provided as the data is oversampled at the D<11:0> pins using
the system clock (SYSCLK). The TxENABLE pin is required
to frame the data burst as the rising edge of TxENABLE is used
to synchronize the AD9856 to the input data rate. The AD9856
registers the input data at the approximate center of the data
valid time. It should be obvious that for larger CIC interpola-
tion rates, more SYSCLK cycles are available to oversample
the input data, maximizing clock jitter tolerances.
For continuous mode input timing, the TxENABLE pin can be
thought of as a data input clock running at 1/2 the input sample
rate (fW/2). In addition to synchronization, for continuous mode
timing, the TxENABLE input indicates to the AD9856 whether
an I or Q input is being presented to the D<11:0> pins. It is
intended that data is presented in alternating fashion such that I
data is followed by Q data. Stated another way, the TxENABLE
pin should maintain approximately a 50/50 duty cycle. As in
burst mode, the rising edge of TxENABLE synchronizes the
AD9856 to the input data rate and the data is registered at the
approximate center of the data valid time. The continuous oper-
ating mode can only be used in conjunction with the full word
input format.
Burst Mode Input TimingFigures 22–26 describe the input timing relationship between
TxENABLE and the 12-bit input data word for all three input
format modes when the AD9856 is configured for burst input
timing. Also shown in these diagrams is the time-aligned, 12-bit
parallel I/Q data as assembled by the AD9856.
Figure 22 describes the classic burst mode timing, for full word
input mode, in which TxENABLE frames the input data stream.
Note that sequential input of alternating I/Q data, starting with
I data, is required.
The input sample rate for full word mode, when the third half-
band filter is engaged, is given by:
fIN = SYSCLK/4N
where N is the CIC interpolation rate.
The input sample rate for full word mode, when the third half-
band filter is not engaged is given by:
fIN = SYSCLK/2N
where N is the CIC interpolation rate
Figure 23 describes an alternate timing method for TxENABLE
when the AD9856 is configured in full word, burst mode
operation. The benefit of this timing is that the AD9856 will
resynchronize the input sampling logic when the rising edge of
TxENABLE is detected. The low time on TxENABLE is lim-
ited to one input sample period and must be low during the Q
data period. The maximum high time on TxENABLE is unlim-
Figure 24 describes the input timing for half word mode, burst
input timing operation.
In half word mode, data is input on the D<11:6> inputs. The
D<5:0> inputs are unused in this mode and should be tied to
DGND or DVDD. The AD9856 expects the data to be input in
the following manner: I<11:6>,I<5:0>,Q<11:6>,Q<5:0>.
Data is twos complement, the sign bit is D<11> in notation
I<11:0>,Q<11:0>.
The input sample rate for half word mode, when the third half-
band filter is engaged, is given by:
fIN = SYSCLK/2N
where N is the CIC interpolation rate.
The input sample rate for half word mode, when the third half-
band filter is not engaged is given by:
fIN = SYSCLK/N
where N is the CIC interpolation rate.
Figure 25 describes the input timing for quarter word, burst
input timing operation.
In quarter word mode, data is input on the D<11:9> inputs.
The D<8:0> inputs are unused in this mode and should be tied
to DGND or DVDD. The AD9856 expects the data to be input
in the following manner: I<11:9>, I<8:6>, I<5:3>, I<2:0>,
Q<11:9>, Q<8:6>, Q<5:3>, Q<2:0>. Data is twos comple-
ment, the sign bit is D<11> in notation I<11:0>, Q<11:0>.
The input sample rate for quarter word mode, when the third
half-band filter is engaged, is given by:
fIN = SYSCLK/N
where N is the CIC interpolation rate.
Please note that Half-Band Filter #3 must be engaged when operat-
ing in quarter word mode.
TxENABLE
D(11:0)
INTERNAL I
INTERNAL QFigure 22.12-Bit Input Mode, Classic Burst Timing
TxENABLE
D(11:0)
INTERNAL I
INTERNAL QFigure 23.12-Bit Input Mode, Alternate TxENABLE Timing
TxENABLE
D(11:6)
INTERNAL I
INTERNAL QFigure 24.6-Bit Input Mode, Burst Mode Timing
TxENABLE
D(11:9)
INTERNAL I
AD9856
TxENABLE
D(11:0)
INTERNAL I
INTERNAL QFigure 26. Burst Mode Input Timing—End of Burst
TxENABLE
D(11:0)
INTERNAL I
INTERNAL QFigure 27.Continuous Mode Input Timing—TxENABLE Static High
TxENABLE
D(11:0)
INTERNAL I
INTERNAL QFigure 28.Continuous Mode Input Timing—TxENABLE Static Low
Figure 26 describes the end of burst timing and internal data
assembly. It’s important to note that in burst mode operation, if
the TxENABLE input is low for more than one input sample
period, numerical zeros are internally generated and passed to
the data path logic for signal processing. This is not valid for
continuous mode operation, as will be discussed later.
To ensure proper operation, the minimum time between falling
and rising edges of TxENABLE is one input sample period.
Continuous Mode Input TimingThe AD9856 is configured for continuous mode input timing by
writing the Continuous Mode bit true (Logic 1). The Continu-
ous Mode bit is in register address 01h, Bit 6. The AD9856
must be configured for full word input format when operating in
continuous mode input timing. The input data rate equations
described above, for full word mode, apply for continuous mode.
Figure 23, which is the alternate burst mode timing diagram, is
also the continuous mode input timing. Figures 27 and 28 de-
scribe what the internal data assembler will present to the signal
processing logic when the TxENABLE input is held static for
greater than one input sample period. Please note that the tim-
ing diagram of Figures 27 and 28 detail INCORRECT timing
relationships between TxENABLE and data. They are only
presented to indicate that the AD9856 will resynchronize
properly after detecting a rising edge of TxENABLE. It should
also be noted that the significant difference between burst and
continuous mode operation is that in addition to synchronizing
the data, TxENABLE is used to indicate whether an I or Q
input is being sampled.
Do not engage continuous mode simultaneously with the
REFCLK multiplier function. This has been found to corrupt
the CIC interpolating filter, forcing unrecoverable mathematical
overflow that can only be resolved by issuing a RESET com-
mand. The problem is due to the PLL failing to be locked to the
reference clock while nonzero data is being clocked into the
interpolation stages from the data inputs. The recommended
sequency is to first engage the REFCLK multiplier function
(allowing at least 1 ms for loop stabilization) and then engage
continuous mode via software.
