AD9852 ,CMOS 300 MHz Complete-DDS SynthesizerOVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 THERMALLY ENHAN ..
AD9852ASQ ,CMOS 300 MHz Complete-DDSGENERAL DESCRIPTIONLinear or Nonlinear FM Chirp Functions with SingleThe AD9852 digital synthesizer ..
AD9852AST ,CMOS 300 MHz Complete-DDSCHARACTERISTICSLogic “1” Voltage, High Z Load FULL VI 3.10 3.10 VLogic “0” Voltage, High Z Load FUL ..
AD9852ASTZ , CMOS 300 MSPS Complete DDS
AD9853AS ,Programmable Digital OPSK/16-QAM ModulatorSpecifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS*EXPLANATION OF TEST LEVELS ..
AD9854ASQ ,CMOS 300 MHz Quadrature Complete-DDSCHARACTERISTICSI and Q DAC Quad. Phase Error 25
AD9852
CMOS 300 MHz Complete-DDS Synthesizer
REV.B
CMOS 300 MSPS
Complete-DDS
FUNCTIONAL BLOCK DIAGRAM
FEATURES
300 MHz Internal Clock Rate
FSK, BPSK, PSK, CHIRP, AM Operation
Dual Integrated 12-Bit D/A Converters
Ultrahigh-Speed Comparator, 3 ps RMS Jitter
Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz
(�1 MHz) AOUT
4� to 20� Programmable Reference Clock Multiplier
Dual 48-Bit Programmable Frequency Registers
Dual 14-Bit Programmable Phase Offset Registers
12-Bit Amplitude Modulation and Programmable
Shaped On/Off Keying Function
Single Pin FSK and BPSK Data Interface
PSK Capability Via I/O Interface
Linear or Nonlinear FM Chirp Functions with Single
Pin Frequency “Hold” Function
Frequency-Ramped FSK
<25 ps RMS Total Jitter in Clock Generator Mode
Automatic Bidirectional Frequency Sweeping
SIN(x)/x Correction
Simplified Control Interface
10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible, or
100 MHz Parallel 8-Bit Programming
3.3 V Single Supply
Multiple Power-Down Functions
Single-Ended or Differential Input Reference Clock
Small 80-Lead LQFP Packaging
APPLICATIONS
Agile, L.O. Frequency Synthesis
Programmable Clock Generator
FM Chirp Source for Radar and Scanning Systems
Test and Measurement Equipment
Commercial and Amateur RF Exciter
GENERAL DESCRIPTIONThe AD9852 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with an internal
high-speed, high-performance D/A converter to form a digitally
programmable agile synthesizer function. When referenced to
an accurate clock source, the AD9852 generates a highly stable,
frequency-phase-amplitude-programmable cosine output that
can be used as an agile L.O. in communications, radar, and many
other applications. The AD9852’s innovative high-speed DDS
core provides 48-bit frequency resolution (1 microHertz tuning
resolution with 300MHz SYSCLK). Maintaining 17bits assures
excellent SFDR. The AD9852’s circuit architecture allows the
generation of output signals at frequencies up to 150 MHz,
(continued on page 15)
AD9852FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . .1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . .2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . .5
Test Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .5
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .6
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . .8
TYPICAL PERFORMANCE CHARACTERISTICS . . . . .9
TYPICAL APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . .13
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
DESCRIPTION OF AD9852 MODES OF OPERATION . .15
Single-Tone (Mode 000) . . . . . . . . . . . . . . . . . . . . . . . . .15
Unramped FSK (Mode 001) . . . . . . . . . . . . . . . . . . . . . .15
Ramped FSK (Mode 010) . . . . . . . . . . . . . . . . . . . . . . . .16
Chirp (Mode 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Basic FM Chirp Programming Steps . . . . . . . . . . . . . . . .19
BPSK (Mode 100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
USING THE AD9852 . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Internal and External Update Clock . . . . . . . . . . . . . . . . .21
Shaped On/Off Keying . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Cosine DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Control DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Inverse SINC Function . . . . . . . . . . . . . . . . . . . . . . . . . .23
REFCLK Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PROGRAMMING THE AD9852 . . . . . . . . . . . . . . . . . . .24
Parallel I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Serial Port I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . .25
GENERAL OPERATION OF THE
SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . .27
Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Serial Interface Port Pin Description . . . . . . . . . . . . . . . .28
Notes on Serial Port Operation . . . . . . . . . . . . . . . . . . . .28
MSB/LSB TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Control Register Description . . . . . . . . . . . . . . . . . . . . . .29
POWER DISSIPATION AND
THERMAL CONSIDERATIONS . . . . . . . . . . . . . . . . .29
THERMAL IMPEDANCE . . . . . . . . . . . . . . . . . . . . . . . . .30
JUNCTION TEMPERATURE CONSIDERATIONS . . . .31
EVALUATION OF OPERATING CONDITIONS . . . . . .31
THERMALLY ENHANCED PACKAGE
MOUNTING GUIDELINES . . . . . . . . . . . . . . . . . . . .32
EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . .33
EVALUATION BOARD INSTRUCTIONS . . . . . . . . . . .33
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
GENERAL OPERATING INSTRUCTIONS . . . . . . . . . .33
Clock Input, J25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Three-State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Low-Pass Filter Testing . . . . . . . . . . . . . . . . . . . . . . . . . .34
Observing the Unfiltered IOUT1 and the
Unfiltered IOUT2 DAC Signals . . . . . . . . . . . . . . . . . .34
Observing the Filtered IOUT1 and the
Filtered IOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Observing the Filtered IOUT1 and the
Filtered IOUT1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
To Connect High-Speed Comparator . . . . . . . . . . . . . . .34
Single-Ended Configuration . . . . . . . . . . . . . . . . . . . . . . .34
USING THE PROVIDED SOFTWARE . . . . . . . . . . . . . .35
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .42
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
TABLE OF CONTENTS
AD9852
(VS = 3.3 V � 5%, RSET = 3.9 k� external reference clock frequency = 30 MHz with REFCLK
Multiplier enabled at 10� for AD9852ASQ, external reference clock frequency = 20 MHz with REFCLK Multiplier enabled at 10�
for AD9852AST unless otherwise noted.)
SPECIFICATIONS
AD9852–SPECIFICATIONS(continued)SERIAL I/O TIMING CHARACTERISTICS
AD9852
EXPLANATION OF TEST LEVELS
Test Level100% Production Tested.
III.Sample Tested Only.
IV.Parameter is guaranteed by design and characterization testing.Parameter is a typical value only.
VI.Devices are 100% production tested at 25°C and guaranteed
by design and characterization testing for industrial
operating temperature range.
ABSOLUTE MAXIMUM RATINGS*Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Maximum Clock Frequency (ASQ) . . . . . . . . . . . . . 300 MHz
Maximum Clock Frequency (AST) . . . . . . . . . . . . . 200 MHz
θJA (ASQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16°C/W
θJC (ASQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2°C/W
θJA (AST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38°C/W
*Absolute maximum ratings are limiting values, to be applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied. Exposure of absolute maximum
rating conditions for extended periods of time may affect device reliability.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
NOTESThe reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied VDD or a 3 V TTL-level pulse input.An internal 800 mV p-p differential voltage swing equates to 400 mV p-p applied to both REFCLK input pins.Pipeline delays of each individual block are fixed; however, if the eight top MSBs of a tuning word are all zeros, the delay will appear longer. This is due to
insufficient phase accumulation per a system clock period to produce enough LSB amplitude to the D/A converter.If a feature such as inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay will be reduced by that amount.The I/O Update CLK transfers data from the I/O Port Buffers to the Programming Registers. This transfer takes system clocks to perform.Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.Represents comparator’s inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device Wavecrest DTS – 2075.Comparator input originates from analog output section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50Ω.Avoid overdriving digital inputs. (Refer to equivalent circuits in Figure 1.)Simultaneous operation at the maximum ambient temperature of 85°C and the maximum internal clock frequency of 200MHz for the 80-lead LQFP, or
300MHz for the thermally-enhanced 80-lead LQFP may cause the maximum die junction temperature of 150°C to be exceeded. Refer to the section titled Power
Dissipation and Thermal Considerations for derating and thermal management information.All functions engaged.All functions except inverse sinc engaged.All functions except inverse sinc and digital multipliers engaged.
Specifications subject to change without notice.
