AD9845BJST-AD9845BJSTZ Fast Delivery |IC PHOENIX CO.,LIMITED

AD9845BJST ,Complete 12-Bit 30 MSPS CCD Signal Processorfeatures a 30 MHz single-channel architec-30 MSPS Correlated Double Sampler (CDS) ture designed to ..
AD9845BJSTZ ,Complete 12-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONS MIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotesPOWER CONSUMPTION 153 mW See ..
AD9846A ,Complete 10-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotePOWER CONSUMPTION 117 mW See TP ..
AD9846AJST ,Complete 10-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotePOWER CONSUMPTION 117 mW See TP ..
AD9846AJSTRL ,Complete 10-Bit 30 MSPS CCD Signal ProcessorAPPLICATIONSpower-down modes.Digital Still CamerasDigital Video CamcordersThe AD9846A operates from ..
AD9846AJSTRL ,Complete 10-Bit 30 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotePOWER CONSUMPTION 117 mW See TP ..
ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet. Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
ADSP-2101BS-100 ,ADSP-2100 Family DSP Microcomputersfeatures plus 80K bytes of on-chip RAMand, on the ADSP-2111, a host interface port.configured as 16 ..
ADSP-2101BS-66 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..

AD9845BJST-AD9845BJSTZ
Complete 12-Bit 30 MSPS CCD Signal Processor
REV.A
Complete 12-Bit 30 MSPS
CCD Signal Processor
FEATURES
Pin Compatible with AD9845A Designs
12-Bit 30 MSPS A/D Converter
30 MSPS Correlated Double Sampler (CDS)
4 dB � 6 dB 6-Bit Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Preblanking Function
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power: 153 mW @ 3V Supply
Space-Saving 48-Lead LQFP Package
APPLICATIONS
High Performance Digital Still Cameras
Industrial/Scientific Imaging
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHPDOUT
AUX2IN
CLPDM
CCDIN
AUX1IN
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
SDATASCKSL VD
VRTVRB
CLPOB
PBLK
GENERAL DESCRIPTION
The AD9845B is an improved version of the AD9845A CCD
signal processor. It features a 30 MHz single-channel architec-
ture designed to sample and condition the outputs of interlaced
and progressive scan area CCD arrays. The AD9845B’s signal
chain consists of an input clamp, a correlated double sampler
(CDS), PxGA, a digitally controlled VGA, a black level clamp,
and a 12-bit A/D converter. Additional input modes are also
provided for processing analog video signals.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input configuration, and
power-down modes.
The AD9845B operates from a single 3 V power supply, typi-
cally dissipates 153 mW, and is packaged in a 48-lead LQFP.
AD9845B–SPECIFICATIONS
GENERAL SPECIFICATIONS
POWER SUPPLY VOLTAGE
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Specifications subject to change without notice.
(DRVDD = 2.7 V, CL = 20 pF, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
AD9845B
PIXEL GAIN AMPLIFIER (PxGA)
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
SYSTEM PERFORMANCE
NOTESInput signal characteristics defined as follows:PxGA gain fixed at Code 63 (3.3 dB).
Specifications subject to change without notice.
CCD MODE SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 30 MHz, unless otherwise noted.)
AD9845B
AUX1 MODE SPECIFICATIONS
Specifications subject to change without notice.
AUX2 MODE SPECIFICATIONS
ACTIVE CLAMP
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 30 MHz, unless otherwise noted.)
AD9845B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
TIMING SPECIFICATIONS
Parameter
SAMPLE CLOCKS
DATA OUTPUTS
SERIAL INTERFACE
*Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
(CL = 20 pF, fSAMP = 30 MHz, CCD Mode Timing in Figures 5 and 6, AUX Mode Timing in Figure 7,
Serial Timing in Figures 21–24.)
ABSOLUTE MAXIMUM RATINGS
Parameter
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB
BYP1-3, CCDIN
Junction Temperature
Lead Temperature (10 sec)
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP PackageqJA = 56∞C/W*
*qJA is measured using a 4-layer PCB.
AD9845B
PIN CONFIGURATION
AUX1IN
AVSS
AUX2IN
AVDD2
BYP3
CCDIN
(LSB) D0
NC = NO CONNECT
D10
BYP2
BYP1
AVDD1
AVSS
(MSB) D11AVSS
SCKSDATASLSTBYNCDVSSDVDD2VRBVRTNC
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
PBLK
CLPOB
SHPSHD
CLPDMNC
PIN FUNCTION DESCRIPTIONS
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every code
must have a finite width. No missing codes guaranteed to 12-bit
resolution indicates that all 4096 codes, must be present over
all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to
the peak deviation of the output of the AD9845B from a true
straight line. The point used as “zero scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as a
Level 1, 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship
1 LSB = (ADC Full Scale/2N codes)
where N is the bit resolution of the ADC. For the AD9845B,
1 LSB is approximately 488 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a high frequency disturbance on the
AD9845B’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Internal Delay for SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9845B
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
Figure 1.Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, and SL
DVDD
DRVDD
THREE-
STATE
DATA
DOUT
Figure 3.CCDIN (Pin 30)
AD9845B–Typical Performance Characteristics
TPC 1.Power vs. Sample Rate
TPC 2.Typical DNL Performance
TPC 3.Output Noise vs. VGA Gain
CCD MODE AND AUX MODE TIMING
Figure 5.CCD Mode Timing
Figure 6.Typical CCD Mode Line Clamp Timing
AD9845B
PIXEL GAIN AMPLIFIER (PxGA) TIMING
Figure 8.PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
Figure 9.PxGA Mode 1 (Mosaic Separate) Detailed Timing
Figure 10.PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
Figure 12.PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
Figure 13.PxGA Mode 3 (3-Color) Detailed Timing
Figure 14.PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
Figure 15.PxGA Mode 4 (4-Color) Detailed Timing
AD9845B
Figure 16.PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
Figure 17.PxGA Mode 5 (VD Selected) Detailed Timing
Figure 18.PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
Figure 19.PxGA Mode 6 (Mosaic Repeat) Detailed Timing

Partno	Mfg	Dc	Qty	Available	Descript
AD9845BJST	ADI	N/a	2	avai	Complete 12-Bit 30 MSPS CCD Signal Processor
AD9845BJSTZ	ADI	N/a	2	avai	Complete 12-Bit 30 MSPS CCD Signal Processor