AD9840AJST Fast Delivery |IC PHOENIX CO.,LIMITED

AD9840AJST ,Complete 10-Bit 40 MSPS CCD Signal ProcessorAPPLICATIONSThe AD9840A operates from a 3 V power supply, typicallyDigital Video Camcordersdissipat ..
AD9840AJST ,Complete 10-Bit 40 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHDParameter Min Typ Max Unit NotesPOWER CONSUMPTION 155 mWMAXIMU ..
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AD9840AJST
Complete 10-Bit 40 MSPS CCD Signal Processor
REV. 0
Complete 10-Bit 40 MSPS
CCD Signal Processor
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHPDOUT
AUX2IN
CLPDM
CCDIN
PBLK
AUX1IN
VRT
VRB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
CML
SDATASCKSL
CLPOB
FEATURES
40 MSPS Correlated Double Sampler (CDS)dB � 6 dB Variable CDS Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 40 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 155 mW @ 3.0 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Video Camcorders
Digital Still Cameras
Industrial Imaging
PRODUCT DESCRIPTION
The AD9840A is a complete analog signal processor for CCD
applications. It features a 40 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9840A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 10-bit A/D converter. Additional input modes are
provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.
The AD9840A operates from a 3 V power supply, typically
dissipates 155 mW, and is packaged in a 48-lead LQFP.
AD9840A–SPECIFICATIONS
GENERAL SPECIFICATIONS
POWER SUPPLY VOLTAGE
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
LOGIC OUTPUTS
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)
AD9840A
VARIABLE GAIN AMPLIFIER (VGA)
BLACK LEVEL CLAMP
SYSTEM PERFORMANCE
NOTESInput Signal Characteristics defined as follows, with 4 dB CDS gain:
Specifications subject to change without notice.
CCD-MODE SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 40 MHz, unless otherwise noted.)
AD9840A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS
Specifications subject to change without notice.
AUX2-MODE SPECIFICATIONS
ACTIVE CLAMP
Specification subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
TIMING SPECIFICATIONS
SERIAL INTERFACE
NOTESMinimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9840A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
(CL = 20 pF, fSAMP = 40 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 8–10.)
ABSOLUTE MAXIMUM RATINGS
CLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-4, CCDIN
Junction Temperature
Lead Temperature
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 92°C
AD9840A
PIN CONFIGURATION
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
CCDIN
DRVSS
DRVSS
(LSB) D0
NC = NO CONNECT
BYP2
BYP1
AVDD1
AVSS
D7
AVSS
SCKSDATASLNCSTBYNCTHREE-STATEDVSSDVDD2VRBVRTCML
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
DVSSPBLK
CLPOB
SHPSHD
CLPDM
DVSS
(MSB) D9
PIN FUNCTION DESCRIPTIONS
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 10-bit
resolution indicates that all 1024 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9840A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level
1, 1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the true
straight line. The error is then expressed as a percentage of the 2 V
ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2N codes) when N is the bit resolution of the
ADC. For the AD9840A, 1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high-frequency disturbance on the
AD9840A’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9840A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
Figure 1.Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DRVDD
THREE-
STATE
DATA
DOUT
Figure 3.CCDIN (Pin 30)
Figure 4.SDATA (Pin 47)
AD9840A
CCD-MODE AND AUX-MODE TIMING
Figure 5.CCD-Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
CLPDM
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKINGDUMMY PIXELSEFFECTIVE PIXELS
PBLK
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
OUTPUT
DATA
Figure 6.Typical CCD-Mode Line Clamp Timing
Figure 7.AUX-Mode Timing

Partno	Mfg	Dc	Qty	Available	Descript
AD9840AJST	AD	N/a	20	avai	Complete 10-Bit 40 MSPS CCD Signal Processor
AD9840AJST	ADI	N/a	7	avai	Complete 10-Bit 40 MSPS CCD Signal Processor