AD9814JR ,Complete 14-Bit CCD/CIS Signal Processorfeatures a 3-channel architecture de-3-Channel Operation Up to 10 MSPS signed to sample and conditi ..
AD9814JR ,Complete 14-Bit CCD/CIS Signal ProcessorSpecifications.2The Gain Error specification is dominated by the tolerance of the internal differen ..
AD9814JRRL ,Low Power 14-Bit, 3-Channel CCD Signal Processor with Progammable Serial Interface and Byte-Wide Data Output FormatSPECIFICATIONS (T to T , AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, f = 6 MHz, f = f =MIN MAX A ..
AD9814KR ,Complete 14-Bit CCD/CIS Signal ProcessorSPECIFICATIONS (T to T , AVDD = +5 V, DRVDD = +5 V)MIN MAXParameter Symbol Min Typ Max UnitsCLOCK P ..
AD9814KR ,Complete 14-Bit CCD/CIS Signal ProcessorAPPLICATIONScally consumes 330 mW of power, and is packaged in a 28-leadFlatbed Document ScannersSO ..
AD9814KR ,Complete 14-Bit CCD/CIS Signal ProcessorSPECIFICATIONS (T to T , AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, f = 6 MHz, f = f =MIN MAX A ..
ADS930 ,8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTERADS930EADS930SBAS059A – MARCH 2001 8-Bit, 30MHz Sampling TM ANALOG-TO-DIG ..
ADS930E ,8-Bit/ 30MHz Sampling ANALOG-TO-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATIC+V .... +6VSAnalog Input ....... +V +0.3VS DISCHARGE SENSITIVITYLogic I ..
ADS930EG4 ,8-Bit, 30 MSPS ADC SE/Diff Inputs w/ Internal Ref. and Low Power, Powerdown 28-SSOP ELECTRICAL CHARACTERISTICSAt T = +25°C, V = +3V, Single-ended Input and Sampling Rate = 30MHz, unle ..
ADS931E ,SpeedPlus 8-Bit, 30MHz Sampling Analog-To-Digital ConverterMAXIMUM RATINGSELECTROSTATIC+V .... +6VSDISCHARGE SENSITIVITYAnalog Input ..... (–0.3V) to (+V +0.3 ..
ADS931EG4 ,8-Bit, 30 MSPS ADC SE/Diff Inputs w/ External Ref. and Low Power, Powerdown 28-SSOP ADS931EADS931SBAS060A – MAY 2001TM 8-Bit, 33MHz Sampling ANALOG-TO-DIGITAL ..
ADSP/2101KG/66 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
AD9814JR-AD9814KR
Complete 14-Bit CCD/CIS Signal Processor
REV. 0
Complete 14-Bit
CCD/CIS Signal Processor
FUNCTIONAL BLOCK DIAGRAM
DRVDDDRVSSAVDDAVSSCAPTCAPBAVDDAVSSCML
OEB
DOUT
SCLK
SLOAD
SDATA
ADCCLKCDSCLK2CDSCLK1
OFFSET
VINB
VING
VINR
FEATURES
14-Bit 10 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel Operation Up to 10 MSPS
1-Channel Operation Up to 7 MSPS
Correlated Double Sampling
1-6x Programmable Gain6300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output (8+6 Format)
3-Wire Serial Digital Interface
+3/+5 V Digital I/O Compatibility
28-Lead SOIC Package
Low Power CMOS: 330 mW (Typ)
Power-Down Mode: <1 mW
APPLICATIONS
Flatbed Document Scanners
Film Scanners
Digital Color Copiers
Multifunction Peripherals
PRODUCT DESCRIPTIONThe AD9814 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture de-
signed to sample and condition the outputs of trilinear color
CCD arrays. Each channel consists of an input clamp, Corre-
lated Double Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), multiplexed to a high performance 14-
bit A/D converter.
The CDS amplifiers may be disabled for use with sensors such
as Contact Image Sensors (CIS) and CMOS active pixel sen-
sors, which do not require CDS.
The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal regis-
ters are programmed through a 3-wire serial interface, and pro-
vide adjustment of the gain, offset, and operating mode.
The AD9814 operates from a single +5 V power supply, typi-
cally consumes 330 mW of power, and is packaged in a 28-lead
SOIC.
AD9814–SPECIFICATIONS
ANALOG SPECIFICATIONSDifferential VREF (@ +25°C)
POWER SUPPLIES
(TMIN to TMAX, AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, fADCCLK = 6 MHz, fCDSCLK1 = fCDSCLK2 =
2 MHz, PGA Gain = 1, Input Range = 4 V, unless otherwise noted.)
AD9814
DIGITAL SPECIFICATIONSSpecifications subject to change without notice.
TIMING SPECIFICATIONS
(TMIN to TMAX, AVDD = +5 V, DRVDD = +5 V, CDS Mode, fADCCLK = 6 MHz, fCDSCLK1 = fCDSCLK2 = 2 MHz,
CL = 10 pF, unless otherwise noted.)
(TMIN to TMAX, AVDD = +5 V, DRVDD = +5 V)NOTESThe Integral Nonlinearity in measured using the “fixed endpoint” method, NOT using a “best-fit” calculation. See Definitions of Specifications.The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.Linear input signal range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9814’s input clamp. A larger reset transient can be tolerated
by using the 3 V clamp level instead of the nominal 4 V clamp level. Linear input signal range will be from 0 V to 3 V when using the 3 V clamp level.
1V TYP
RESET TRANSIENT
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)
4V p-p MAX INPUT SIGNAL RANGE
GNDThe input limits are defined as the maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of the device.
Signals beyond the input limits will turn on the overvoltage protection diodes.The PGA Gain is approximately “linear in dB” and follows the equation:
Specifications subject to change without notice.
AD9814
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS*Storage Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance28-Lead 300 Mil SOICJA = 71.4°C/WJC = 23°C/W
PIN CONFIGURATION
CDSCLK1AVDD
CDSCLK2AVSS
ADCCLKVINR
OEBOFFSET
DRVDDVING
DRVSSCML
(MSB) D7VINBCAPTCAPBAVSSAVDDSLOADSCLK
(LSB) D0SDATA
PIN FUNCTION DESCRIPTIONSTYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO =
Digital Output, P = Power.
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)Integral nonlinearity error refers to the deviation of each indi-
vidual code from a line drawn from “zero scale” through “posi-
tive full scale.” The point used as “zero scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
14-bit resolution indicates that all 16384 codes, respectively,
must be present over all operating ranges.
OFFSET ERRORThe first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the ideal
level.
GAIN ERRORThe last code transition should occur for an analog value
1 1/2 LSB below the nominal full-scale voltage. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between the first and last
code transitions.
INPUT REFERRED NOISEThe rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in
LSB, and converted to an equivalent voltage, using the relation-
ship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred
to the input of the AD9814 by dividing by the PGA gain.
CHANNEL-TO-CHANNEL CROSSTALKIn an ideal three channel system, the signal in one channel will
not influence the signal level of another channel. The channel-
to-channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9814, one channel is grounded and the other two chan-
nels are exercised with full-scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The differ-
ence is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAYThe aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9814 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
POWER SUPPLY REJECTIONPower Supply Rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
AD9814
PIXEL N (R, G, B)
tAD
tC2
tC2ADF
tADC2tC2ADRtADCLK
tADCLKtOD
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
R (N–2)G (N–2)G (N–2)B (N–2)B (N–2)R (N–1)R (N–1)G (N–1)G (N–1)B (N–1)
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
tADC1
tAD
tC1
CDSCLK1Figure 1.3-Channel CDS Mode Timing
tAD
ANALOG
INPUTS
tOD
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
tC1C2
tC1
CDSCLK1
HIGH BYTELOW BYTELOW BYTEHIGH BYTEFigure 2.1-Channel CDS Mode Timing
PIXEL N (R, G, B)
tC2
tADC2tOD
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTEFigure 3.3-Channel SHA Mode Timing
tOD
ANALOG
INPUTS
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
PIXEL N
HIGH BYTELOW BYTELOW BYTEHIGH BYTEFigure 4.1-Channel SHA Mode Timing
AD9814
tHZ
tODtOD
ADCCLK
OUTPUT
DATA
OEB
PIXEL NPIXEL NFigure 5.Digital Output Data Timing
SDATA
SCLK
SLOAD
tDStDH
tLStLHFigure 6.Serial Write Operating Timing
SDATA
SCLK
SLOAD
tDStRDVtDH
tLStLHFigure 7.Serial Read Operation Timing
