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AD9804AJSTADN/a1550avaiComplete 10-Bit, 18 MHz CCD Signal Processor


AD9804AJST ,Complete 10-Bit, 18 MHz CCD Signal ProcessorSPECIFICATIONS L CLKParameter Symbol Min Typ Max UnitSAMPLE CLOCKSDATACLK, SHP, SHD Clock Period t ..
AD9804JST ,Complete 10-Bit 18 MSPS CCD Signal ProcessorSPECIFICATIONSMIN MAX DATACLK SHP SHD Parameter Min Typ Max UnitTEMPERATURE RANGEOperating –20 +85 ..
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ADS8519IDB ,16-Bit 250kHz CMOS Analog-to-Digital Converter w/Serial Interface 4.096V Internal Reference 28-SSOP -40 to 85MAXIMUM RATINGSOver operating free-air temperature range (unless otherwise noted).UNITR1 ±25VINR2 ± ..
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AD9804AJST
Complete 10-Bit, 18 MHz CCD Signal Processor
REV.0
Complete 10-Bit 18 MSPS
CCD Signal Processor
FUNCTIONAL BLOCK DIAGRAM
SDATASCKSL
DATACLKSHDSHP
DOUTVRB
DVDD
DVSS
DRVDD
DRVSS
CML
CLPOB
AVDDPBLK
AVSS
CLPDM
CCDIN
FEATURES
18 MSPS Correlated Double Sampler (CDS)
6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Preblanking Function
10-Bit 18 MSPS A/D Converter
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power CMOS
48-Lead LQFP Package
APPLICATIONS
PC Cameras
Digital Still Cameras
PRODUCT DESCRIPTION

The AD9804 is a complete analog signal processor for CCD
applications. It features an 18 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9804’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled VGA, black level clamp, and a 10-bit A/D
converter. The internal VGA gain register is programmed through
a 3-wire serial digital interface.
AD9804–SPECIFICATIONS
ANALOG SPECIFICATIONS

NOTESInput signal characteristics defined as follows:
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 18 MHz, unless otherwise noted.)
DIGITAL SPECIFICATIONS

LOGIC OUTPUTS
(DRVDD = 2.7 V, CL = 20 pF.)
AD9804
TIMING SPECIFICATIONS

DATA OUTPUTS
NOTESMinimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice
(CL = 20 pF, fCLK = 18 MHz, timing shown in Figures 1 and 2.)
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9804 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
ORDERING GUIDE
THERMAL CHARACTERISTICS
Thermal Resistance

48-Lead LQFP Package
θJA = 92°C/W
AD9804
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
AVSS
AVDD
BYP4
CCDIN
(LSB) D0
NC = NO CONNECT
BYP2
BYP1
AVDD
AVSS
(MSB) D9AVSS
SCKSDATASLNCDVSSRSTBDVSSDVSSDVDDVRBVRTCML
DRVDDDRVSS
DVSS
DATACLK
DVDD
PBLK
CLPOB
SHP
SHD
CLPDM
TIMING DIAGRAMS
Figure 1.Pixel Rate Timing
Figure 2.Typical Line Clamp Timing
AD9804
PROGRAMMING THE SERIAL INTERFACE
Table I.VGA Gain Register Contents (Default Value x096)

Figure 3.Serial Write Operation
Figure 4.Serial Readback Operation
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