AD9764AR-AD9764ARU Fast Delivery |IC PHOENIX CO.,LIMITED

AD9764ARU ,14-Bit, 125 MSPS TxDAC D/A ConverterFEATURESMember of Pin-Compatible TxDAC Product Family+5V125 MSPS Update Rate0.1mF14-Bit ResolutionE ..
AD9765AST ,12-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 12 Bits1DC ACCURACYIntegral Linear ..
AD9765ASTZ , 10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters
AD9765ASTZ , 10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters
AD9767AST ,14-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 14 Bits1DC ACCURACYIntegral Linear ..
AD9768JD ,Ultrahigh Speed IC D/A ConverterSPECIFICATIONSinput levels; nominal power supplies; R = 50 V; R = 220 V; V = 0 V)L SET RETParameter ..
ADS8361IDBQR ,Dual/ 500kSPS/ 16-Bit/ 2 + 2 Channel/ Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER.RECOMMENDED OPERATING CONDITIONSCONDITIONS MIN NOM MAX UNITSSupply Voltage, AGND to AV 4.75 5 5.25 ..
ADS8361IDBQRG4 ,16-Bit 500 kSPS 2 ADCs, 4ch, serial out 24-SSOP -40 to 125Maximum Ratings maycause permanent damage to the device. These are stress ratings only, andfunction ..
ADS8361IRHBT ,Dual/ 500kSPS/ 16-Bit/ 2 + 2 Channel/ Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATICAbsolute
ADS8363SRHBR ,16-Bit, 1-MSPS, 4x2/2x2 Simultaneous-Sampling SAR ADC 32-VQFN -40 to 125Block Diagram... 184 Revision HistoryChanges from Revision C (January 2017) to Revision D Page• Cha ..
ADS8363SRHBT ,16-Bit, 1-MSPS, 4x2/2x2 Simultaneous-Sampling SAR ADC 32-VQFN -40 to 125 SBAS523D–OCTOBER 2010–REVISED SEPTEMBER 2017Changes from Revision A (December, 2010) to Revision B ..
ADS8364Y/250 ,16-Bit 250 kSPS 6 ADCs, Parallel Out, W/6 x FIFO W/6 Ch.MAXIMUM RATINGSELECTROSTATICAbsolute

AD9764AR-AD9764ARU
14-Bit, 125 MSPS TxDAC D/A Converter
REV. B
14-Bit, 125 MSPS
TxDAC® D/A Converter
FUNCTIONAL BLOCK DIAGRAMFEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
14-Bit Resolution
Excellent SFDR and IMD
Differential Current Outputs:2 mA to 20 mA
Power Dissipation:190 mW @ 5V to 45mW @ 3V
Power-Down Mode:25 mW @ 5V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages:28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations
ADSL/HFC Modems
Instrumentation
PRODUCT DESCRIPTION
The AD9764 is the 14-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC family, which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs, is specifically opti-
mized for the transmit signal path of communication systems.
All of the devices share the same interface options, small outline
package and pinout, providing an upward or downward compo-
nent selection path based on performance, resolution and cost.
The AD9764 offers exceptional ac and dc performance while
supporting update rates up to 125 MSPS.
The AD9764’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW with a slight degradation in performance
by lowering the full-scale current output. Also, a power-down
mode reduces the standby power dissipation to approximatelymW.
The AD9764 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input
latches and a 1.2 V temperature compensated bandgap refer-
ence have been integrated to provide a complete monolithic
DAC solution. Flexible supply options support +3 V and +5 V
CMOS logic families.
The AD9764 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kW output impedance.
TxDAC is a registered trademark of Analog Devices, Inc.
*Patent pending.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9764 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9764 full-scale current
to be adjusted over a 2mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9764 may operate
at reduced power levels or be adjusted over a 20dB range to
provide additional gain ranging capabilities.
The AD9764 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTSThe AD9764 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.Manufactured on a CMOS process, the AD9764 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance beyond that previously attainable by higher power/cost
bipolar or BiCMOS devices.On-chip, edge-triggered input CMOS latches readily interface
to +3 V and +5 V CMOS logic families. The AD9764 can
support update rates up to 125 MSPS.A flexible single-supply operating range of 2.7V to 5.5 V, and
a wide full-scale current adjustment span of 2mA to 20 mA,
allows the AD9764 to operate at reduced power levels.The current output(s) of the AD9764 can be easily config-
ured for various single-ended or differential circuit topologies.
AD9764–SPECIFICATIONS
DC SPECIFICATIONS
REFERENCE INPUT
TEMPERATURE COEFFICIENTS
NOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32 · the IREF current.Use an external buffer amplifier to drive any external load.Reference bandwidth is a function of external cap at COMP1 pin and signal level.For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 W RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.–5% Power supply variation.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
AD9764
DYNAMIC SPECIFICATIONS
NOTESMeasured single-ended into 50W load.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,V Doubly Terminated, unless otherwise noted)
AD9764
DIGITAL SPECIFICATIONS
Specifications subject to change without notice.
0.1%
0.1%
DB0–DB13
CLOCK
IOUTA
IOUTB
Figure 1. Timing Diagram
ORDERING GUIDE
*R = Small Outline IC, RU = TSSOP.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil SOICJA = 71.4°C/WJC = 23°C/W
28-Lead TSSOPJA = 97.9°C/WJC = 14.0°C/W
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
Lead Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
PIN CONFIGURATION
NC = NO CONNECT
(MSB) DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLOCK
DVDD
DCOM
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
PIN FUNCTION DESCRIPTIONS
AD9764
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied over a specified range.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
RSET
2kV
0.1mF
DVDD
DCOM
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
MINI-CIRCUITS
T1-1T
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
+5V
Figure 2.Basic AC Characterization Test Setup
Typical AC Characterization Curves
(AVDD = +5 V, DVDD = +3 V, IOUTFS = 20 mA, 50V Doubly Terminated Load, Differential Output, TA = +258C, SFDR up to Nyquist, unless otherwise noted)
FREQUENCY – MHz
SFDR – dBc
0.1110010
Figure 3.SFDR vs. fOUT @ 0 dBFS
FREQUENCY – MHz
SFDR – dBc25101520
Figure 6.SFDR vs. fOUT @ 50 MSPS
AOUT – dBFS
SFDR – dBc
–30–250–20–15–10–5
Figure 9.Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
FREQUENCY – MHz
SFDR – dBc0.52.51.01.52.0
Figure 4.SFDR vs. fOUT @ 5MSPS
FREQUENCY – MHz
SFDR – dBc
01050203040
Figure 7.SFDR vs. fOUT @100 MSPS
AOUT – dBFS
SFDR – dBc
–30–250–20–15–10–5
Figure 10.Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
Figure 5.SFDR vs. fOUT @ 25 MSPS
Figure 8.SFDR vs. fOUT and
IOUTFS @ 25MSPS and 0 dBFS
Figure 11.Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
AD9764

dBc
000.0E+040.0E+680.0E+6120.0E+6
–90
Figure 12.THD vs. fCLOCK @
fOUT = 2MHz

CODE
ERROR – LSB
0.5
Figure 15.Typical INL
000.0E+07.5E+615.0E+622.5E+6
10dB – Div
–30
Figure 18.Single-Tone SFDR
fCLOCK – MSPS
SNR – dB101002030405060708090
Figure 13.SNR vs. fCLOCK @ fOUT =
2.0 MHz

CODE
ERROR – LSB
–0.5
Figure 16.Typical DNL
0E+025E+65E+610E+615E+620E+6
10dB – Div
–30
Figure 19.Dual-Tone SFDR

Figure 14.Differential vs. Single-
Ended SFDR vs. fOUT @ 50 MSPS

Figure 17.SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
10dB – Div
000.0E+07.5E+615.0E+622.5E+6
Figure 20.Four-Tone SFDR
FUNCTIONAL DESCRIPTION
Figure 21 shows a simplified block diagram of the AD9764. The
AD9764 consists of a large PMOS current source array that is
capable of providing up to 20mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100kW).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differen-
tial current switches. The switches are based on a new architec-
ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif-
ferential current switches.
The analog and digital sections of the AD9764 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, RSET. The external resistor, in combination with
both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is mirrored over to
the segmented current sources with the proper scaling factor.
The full-scale current, IOUTFS, is 32 times the value of IREF.
DAC TRANSFER FUNCTION
The AD9764 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 16383) while
IOUTB, the complementary output, provides no current. The
IOUTB = (16383 – DAC CODE)/16384 · IOUTFS(2)
where DAC CODE = 0 to 16383 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage
VREFIO and external resistor RSET. It can be expressed as:
IOUTFS = 32 · IREF(3)
where IREF = VREFIO/RSET(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note
that RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminatedW or 75W cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
VOUTA = IOUTA · RLOAD(5)
VOUTB = IOUTB · RLOAD(6)
Note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB is:
VDIFF = (IOUTA – IOUTB) · RLOAD(7)
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
VDIFF = {(2 DAC CODE – 16383)/16384} ·
VDIFF = {(32 RLOAD/RSET) · VREFIO(8)
These last two equations highlight some of the advantages of
operating the AD9764 differentially. First, the differential op-
eration will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (VDIFF) of the
Figure 21.Functional Block Diagram
AD9764
REFERENCE OPERATION
The AD9764 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external
reference. REFIO serves as either an input or output, depending
on whether the internal or external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 22, the internal
reference is activated, and REFIO provides a 1.20V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1mF or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100nA if any
additional loading is required.
+5V
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
Figure 22.Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 23. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1mF compensation capacitor is not required
since the internal reference is disabled, and the high input im-
pedance (i.e., 1 MW) of REFIO minimizes any loading of the
external reference.
AVDD
AVDD
Figure 23.External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9764 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a V-I converter, as shown
in Figure 23, such that its current output, IREF, is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated
in Equation 4. IREF is copied over to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9764, which is pro-
portional to IOUTFS (refer to the Power Dissipation section). The
second benefit relates to the 20dB adjustment, which is useful
for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 1.4 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as a
filter to reduce the noise contribution from the reference ampli-
fier. Figure 24 shows the relationship between the external
capacitor and the small signal –3dB bandwidth of the refer-
ence amplifier. Since the –3dB bandwidth corresponds to the
dominant pole, and hence the time constant, the settling time of
the control amplifier to a stepped reference input response can
be approximated.
Figure 24.External COMP1 Capacitor vs. –3dB Bandwidth
The optimum distortion performance for any reconstructed
waveform is obtained with a 0.1mF external capacitor installed.
Thus, if IREF is fixed for an application, a 0.1mF ceramic chip
capacitor is recommended. Also, since the control amplifier is
optimized for low power operation, multiplying applications
requiring large signal swings should consider using an external
control amplifier to enhance the application’s overall large signal
multiplying bandwidth and/or distortion performance.
There are two methods in which IREF can be varied for a fixed
RSET. The first method is suitable for a single-supply system in
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing IREF to be varied for a fixed RSET. Since the
input impedance of REFIO is approximately 1 MW, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 25 using the AD7524 and an external 1.2 V reference,
the AD1580.
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and IREF is
varied by an external voltage, VGC, applied to RSET via an ampli-
fier. An example of this method is shown in Figure 26 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value of
RSET is such that IREFMAX and IREFMIN do not exceed 62.5mA
and 625mA, respectively. The associated equations in Figure 26
can be used to determine the value of RSET.
AVDD
OPTIONAL
VGC
1mF
WITH VGC < VREFIO AND 62.5mA # IREF # 625A
Figure 26.Dual-Supply Gain Control Circuit
In some applications, the user may elect to use an external
control amplifier to enhance the multiplying bandwidth,
distortion performance and/or settling time. External amplifiers
capable of driving a 50 pF load such as the AD817 are suitable
for this purpose. It is configured in such a way that it is in
parallel with the weaker internal reference amplifier as shown in
Figure 27. In this case, the external amplifier simply overdrives
the weaker reference control amplifier. Also, since the internal
control amplifier has a limited current output, it will sustain no
damage if overdriven.
AVDD
RSET
VREF
INPUT
EXTERNAL
CONTROL AMPLIFIER
ANALOG OUTPUTS
The AD9764 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and
VOUTB, via a load resistor, RLOAD, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, VDIFF, existing between VOUTA and VOUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 28 shows the equivalent analog output circuit of the
AD9764 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
and is typically 100 kW in parallel with 5 pF. Due to the na-
ture of a PMOS device, the output impedance is also slightly
dependent on the output voltage (i.e., VOUTA and VOUTB) and, to
a lesser extent, the analog supply voltage, AVDD, and full-scale
current, IOUTFS. Although the output impedance’s signal depen-
dency can be a source of dc nonlinearity and ac linearity (i.e.,
distortion), its effects can be limited if certain precautions are
noted.
RLOADRLOAD
Figure 28.Equivalent Analog Output Circuit
IOUTA and IOUTB also have a negative and positive voltage compli-
ance range. The negative output compliance range of –1.0V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
1.2V
AVDD
AVDD
DB7–DB0
AD1580
Figure 25.Single-Supply Gain Control Circuit

Partno	Mfg	Dc	Qty	Available	Descript
AD9764AR	ANALOGDEVICE	N/a	16	avai	14-Bit, 125 MSPS TxDAC D/A Converter
AD9764ARU	AD	N/a	50	avai	14-Bit, 125 MSPS TxDAC D/A Converter