AD9761ARSRL ,10-Bit, Complete, 40 MSPS, dual Transmit D/A ConverterSPECIFICATIONSMIN Max OUTFSParameter Min Typ Max UnitRESOLUTION 10 Bits1DC ACCURACY Integral Nonl ..
AD9761ARSZ ,10-Bit, Complete, 40 MSPS, dual Transmit D/A ConverterSPECIFICATIONS50 Doubly Terminated, unless otherwise noted.)Parameter ..
AD9762AR ,12-Bit, 125 MSPS TxDAC D/A ConverterSPECIFICATIONSMIN MAX OUTFS Parameter Min Typ Max UnitsRESOLUTION 12 Bits1DC ACCURACYIntegral Linea ..
AD9763AST ,10-Bit, 125 MSPS Dual TxDAC+ D/A Converterapplications. The digital interface consists oftwo double-buffered latches as well as control logic ..
AD9763AST ,10-Bit, 125 MSPS Dual TxDAC+ D/A ConverterSPECIFICATIONSMIN MAX OUTFSParameter Min Typ Max UnitsRESOLUTION 10 Bits1DC ACCURACYIntegral Linear ..
AD9764AR ,14-Bit, 125 MSPS TxDAC D/A ConverterSPECIFICATIONSParameter Min Typ Max UnitsDYNAMIC PERFORMANCEMaximum Output Update Rate (f ) 125 MSP ..
ADS8344NG4 ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital Converter 20-SSOP -40 to 85Electrical CharacteristicsREFADS8344Table for ranges.CH5 6 15 DOUT12 +V Power Supply, 2.7V to 5VCC1 ..
ADS8345 ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterSBAS177C
ADS8345E ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterELECTRICAL CHARACTERISTICS: +2.7VAt T = –40°C to +85°C, +V = +2.7V, V = +1.25V, f = 100kHz, and f ..
ADS8345E/2K5 ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterMaximum Ratings”tion to complete device failure. Precision integrated circuitsmay cause permanent d ..
ADS8345EB ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterMAXIMUM RATINGSELECTROSTATIC+V to GND –0.3V to +6VCC Analog Inputs to GND ...... –0.3V to (+V ) + ..
ADS8345EB ,16-Bit, 8-Channel Serial Output Sampling Analog-to-Digital ConverterELECTRICAL CHARACTERISTICS: +2.7VAt T = –40°C to +85°C, +V = +2.7V, V = +1.25V, f = 100kHz, and f ..
AD9761ARSRL-AD9761ARSZ
10-Bit, Complete, 40 MSPS, dual Transmit D/A Converter
ANALOG
DEVICES
Dual 10-Bit TxDAC+®
with 2x Interpolation Filters
ADB761
FEATURES
Complete 10-Bit, 40 MSPS DualTransmit DAC
Excellent Gain and Offset Matching
Differential Nonlinearity Error: 0.5 LSB
Effective Number of Bits: 9.5
Signal-to-Noise and Distortion Ratio: 59 dB
Spurious-Free Dynamic Range: 71 dB
2x Interpolation Filters
20 MSPS/Channel Data Rate
Single Supply: 3V to 5.5V
Low Power Dissipation: 93 mW (3V Supply @
40 MSPS)
On-Chip Reference
28-Lead SSOP
PRODUCT DESCRIPTION
The AD9761 is a complete dual-channel, high speed, IO-bit
CMOS DAC. The AD9761 has been developed specifically for
use in wide bandwidth communication applications (e.g., spread
spectrum) where digital I and Q information is being processed
during transmit operations. It integrates two 10-bit, 40 MSPS
DACs, dual 2X interpolation filters, a voltage reference, and digi-
tal input interface circuitry. The AD97 61 supports a 20 MSPS
per channel input data rate that is then interpolated by 2X up to
40 MSPS before simultaneously updating each DAC.
The interleaved I and Q input data stream is presented to the
digital interface circuitry, which consists of I and Q latches as
well as some additional control logic. The data is de-interleaved
back into its original I and Q data. An on-chip state machine
ensures the proper pairing of I and Q data. The data output from
each latch is then processed by a 2X digital interpolation filter
that eases the reconstruction filter requirements. The interpo-
lated output of each filter serves as the input of their respective
lO-bit DAC.
The DACs utilize a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or dif-
ferential applications. Both DACs are simultaneously updated
and provide a nominal full-scale current of 10 mA. Also, the
full-scale currents between each DAC are matched to within
0.07 dB (i.e., 0.75%), thus eliminating the need for additional
gain calibration circuitry.
The AD97 61 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 3 V to 5.5 V and
consumes 200 mW of power. To make the AD9761 complete, it
also offers an internal 1.20V temperature-compensated band gap
reference.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks arethe property oftheir respective companies.
FUNCTIONAL BLOCK DIAGRAM
DCOM DVDD CLOCK ACOM AVDD
V V V V
LATCH -rs, m -N I IOUTA
SLEEP I v -v Ioum
REFERENCE FSADJ
DAC DATA REFIO
INPUTS comm
(10 BITS) BIAS COMP2
GENERATOR comps
"A LATCH -rN 27" -r, o QOUTA
" l "V V DAC ooum
WRITE INPUT MUX
SELECT INPUT CONTROL AD9761
PRODUCT HIGHLIGHTS
1. Dual lO-Bit, 40 MSPS DACs
A pair of high performance 40 MSPS DACs optimized for low
distortion performance provide for flexible transmission of I
and Q information.
2. 2X Digital Interpolation Filters
Dual matching FIR interpolation filters with 62.5 dB stop-
band rejection precede each DAC input, thus reducing the
DACs' reconstruction filter requirements.
3. Low Power
Complete CMOS dual DAC function operates on a low
200 mW on a single supply from 3 V to 5.5 V. The DAC
full-scale current can be reduced for lower power opera-
tion, and a sleep mode is provided for power reduction
during idle periods.
4. On-Chip Voltage Reference
The AD9761 includes a 1.20V temperature-compensated
band gap voltage reference.
5. Single lO-Bit Digital Input Bus
The AD9761 features a flexible digital interface that allows
each DAC to be addressed in a variety of ways including dif-
ferent update rates.
6. Small Package
The AD9761 offers the complete integrated function in a
compact 28-lead SSOP package.
7. Product Family
The AD9761 Dual Transmit DAC has a pair of Dual Receive
ADC companion products, the AD9281 (8 bits) and AD9201
(10 bits).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703 © 2003 Analog Devices, lnc.All rights reserved.
Jllyl781-SPEillFliWlillG
Oil SPECIFICATIONS (ho to u,, AVDD = 5 ll, IWIN = 5 ll, laws: Ill mA, unless otherwise noted.)
Parameter Min Typ Max Unit
RESOLUTION 10 Bits
DC ACCURACY1
Integral Nonlinearity Error (INL)
TA = 25°C -1.75 i0.5 +1.75 LSB
TMIN to TMAX -2.75 i0.7 +2.75 LSB
Differential Nonlinearity (DNL)
TA = 25°C -1 i0.4 +1.25 LSB
TMIN tOTMAX -1 i0.5 +1.75 LSB
Monotonicity (IO-Bit) Guaranteed over Rated Specification Temperature Range
ANALOG OUTPUT
Offset Error -0.05 i0.025 +0.05 % of FSR
Offset Matching between DACs -0. 10 $0.05 +0.10 % of FSR
Gain Error (without Internal Reference) -5.5 i1.0 +5.5 % of FSR
Gain Error (with Internal Reference) -5.5 i1.0 +5.5 % of FSR
Gain Matching between DACs -1.0 i025 +1.0 % of FSR
Full-Scale Output Current2 10 mA
Output Compliance Range -1.0 +1.25 V
Output Resistance 100 kn
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Currents 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 Mn
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift 0 ppm/°C
Gain Drift (without Internal Reference) i50 ppm/°C
Gain Drift (with Internal Reference) i140 ppm/°C
Gain Matching Drift (between DACs) LF25 ppm/°C
Reference Voltage Drift i550 ppm/°C
POWER SUPPLY
Voltage Range 3.0 5.0 5.5 V
Analog Supply Current (IAVDD) 26 29 mA
Voltage Range 2.7 5.0 5.5 V
Digital Supply Current at 5 V (IDVDD)4 15 18 mA
Digital Supply Current at 3 V (IDVDD)4 5 mA
Nominal Power Dissipation5
AVDD and DVDD at 3V 93 mW
AVDD and DVDD at 5 V 200 250 mW
Power Supply Rejection Ratio (PSRR)-AVIDD -0.25 +0.25 % of FSR/V
Power Supply Rejection Ratio (PSRR)-DVIDD -0.02 +0.02 % of FSR/V
OPERATING RANGE -40 +85 °C
1Measured at IOUTA and QOUTA, driving a virtual ground.
2Nominal full-scale current, IouTes, is 16x the IREF current.
3Use an external amplifier to drive any external load.
'Measured at fCLOCK = 40 MSPS and four = 1 MHz.
'Measured as unbuffered voltage output into 50 n RLOAD at IOUTA, IOUTB, QOUTA, and QOUTB; fCLOCK = 40 MSPS and fouT = 8 MHz.
Specifications subject to change without notice.
REV. C
AD97BI
iu, to TMAX, AVDD = 5 ll, DVDD = 5 ll, lows = lil mA, Differential Transformer Coupled Mtput,
DYNAMIC SPEC I Fl CA" (INS 50 n Doubly Terminated, unless otherwise noted.)
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate 40 MSPS
Output Settling Time (tsr to 0.025%) 35 ns
Output Propagation Delay (tpD) 55 Input Clock Cycles
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%) 2.5 ns
Output FallTime (10% to 90%) 2.5 ns
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion (SINAD)
four = 1 MHz; CLOCK = 40 MSPS 56 59 dB
Effective Number of Bits (ENOBs) 9.0 9.5 Bits
Total Harmonic Distortion (THD)
four = 1 MHz; CLOCK = 40 MSPS
TA = 25°C -68 -58 dB
TMIN to TM -67 -53 dB
Spurious-Free Dynamic Range (SFDR)
four = 1 MHz; CLOCK = 40 MSPS; 10 MHz Span 59 68 dB
Channel Isolation
four = 8 MHz; CLOCK = 40 MSPS; 10 MHz Span 90 dBc
Specifications subject to change without notice.
ll I G IThl. SPEC IFI iWI il NS (ho, to Tm, AVDD = 5ll, DVDD = 5 ll, lumps =lllmh unless otherwise noted.)
Parameter
Typ Max
DIGITAL INPUTS
Logic 1Voltage @ DVDD = 5V
Logic 1 Voltage @ DVDD = 3V
Logic 0Voltage @ DVDD = 5V
Logic 0Voltage @ DVDD = 3V
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (ts)
Input Hold Time (tH)
CLOCK High
CLOCK Low
Invalid CLOCK/WRITE Window (tCINV)*
UIUINWUI
aaaaag§§<<<<
'tcuw is an invalid window of 4 ns duration beginning 1 ns after the rising edge of WRITE in which the rising edge of CLOCK must not occur.
Specifications subject to change without notice.
DB9-DB0
INPUTS
SELECT
m IDATA m ODATAm
CLOCK I Fl
NOTE: WRITE AND CLOCK CAN BE
TIED TOGETHER. FOR TYPICAL EXAMPLES,
REFER TO DIGITAL INPUTS AND INTERLEAVED
INTERFACE CONSIDERATION SECTION.
Figure l Timing Diagram
REV. C
AD9761
(ha to har, AVDD = 2.7 ll to 5.5 ll, DVDD = 2.7 ll to 5.5 ll, lows = Ill mA, unless
DIGITAL FILTER SPECIFICATIONS otherwise noted.)
Parameter Min Typ Max Unit
MAXIMUM INPUT CLOCK RATE (fCLOCK) 40 MSPS
DIGITAL FILTER CHARACTERISTICS
Pass Bandwidthl: 0.005 dB 0.2010 fOUT/fCLOCK
Pass Bandwidth: 0.01 dB 0.2025 fOUT/fCLOCK
Pass Bandwidth: 0.1 dB 0.2105 fOUT/fCLOCK
Pass Bandwidth: -3 dB 0.239 fOUT/fCLOCK
Linear Phase (FIR Implementation)
Stop-Band Rejection: 0.3 fCLOCK to 0.7 fCLOCK -62.5 dB
Group Delay2 32 Input Clock Cycles
Impulse Response Duration'
-40 dB 28 Input Clock Cycles
-60 dB 40 Input Clock Cycles
'Excludes SINx/x characteristic of DAC.
2Defined as the number of data clock cycles between impulse input and peak of output response.
355 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update.
Specifications subject to change without notice.
OUTPUT (dBFS)
-100 II I
0 0.1 0.2 0.3 0.4
FREQUENCY RESPONSE (DC to tccotud2)
Figure 2a. FIR Filter Frequency Response
NORMALIZED OUTPUT
5 10 15 20 25 30 35
TIME (Samples)
Figure 2b. FIR Filter Impulse Response
Table I. Integer Filter Coefficients for 43-Tap Half-Band
FIR Filter
Lower Coefficient Upper Coefficient Integer Value
H(l) H(43) 1
H(2) H(42) 0
H(3) H(41) -3
H(4) H(40) O
H(5) H(39) 8
H(6) H(38) 0
H(7) H(37) -1 6
H(8) H(36) 0
H(9) H(35) 29
H(10) H(34) 0
H(l I) H(33) -50
H(12) H(32) 0
H(13) H(31) 81
H(14) H(30) 0
H(15) H(29) -131
H(16) H(28) 0
H(17) H(27) 216
H(18) H(26) 0
H(19) H(25) -400
H(20) H(24) 0
H(21) H(23) 1264
H(22) 1998
-4- REV. C
AD9761
ORDERING GUIDE
Thermal Resistance
Package Package 28-Lead SSOP
Model Description Option 61A = 109°C/W
AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28
AD9761ARSRL 28-Lead Shrink Small Outline (SSOP) RS-28
AD9761-EB Evaluation Board
ABSOLUTE MAXIMUM RATINGS'
THERMAL CHARACTERISTICS
Parameter Respect to Min Max Unit
AVDD ACOM -0.3 +6.5 V
DVDD DCOM -0.3 +6.5 V
ACOM DCOM -0.3 +0.3 V
AVDD DVDD -6.5 +6.5 V
CLOCK,WRITE DCOM -0.3 DVDD + 0.3 V
SELECT, SLEEP DCOM -0.3 DVDD + 0.3 V
Digital Inputs DCOM -0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM -1.0 AVDD + 0.3 V
QOUTA, QOUTB ACOM -1.0 AVDD + 0.3 V
COMPl, COMP ACOM -0.3 AVDD + 0.3 V
COMP3 ACOM -0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM -0.3 AVDD + 0.3 V
REFLO ACOM -0.3 +0.3 V
Junction Temperature 150 °C
Storage Temperature -65 +150 '"C
Lead Temperature (10 sec) 300 ''C
"Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This
is a stress rating only; functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
2.7V TO
Cl +1, j.r,i.., ',.TfFFj..:rus,
DVDD DCOM COMP2 AVDD AVSS COMP1 comps MlNl-CIRCUITS
-r, .-N -ts, r-w""
LATCH I . TO HP3589A
I ' ttxiN -v DAC 1000 E SPECTRUM/NETWORK
I ANALYZER
l l son INPUT
TEKTRONIX 50n 20PF 1 50n 20PF
AWG-2021 _ 1
DIGITAL E E
DATA DB9-DB0 AD9761 I
MINI-CIRCUITS
UN -rs -N, '--(ooI/. g
LATCH _-,N t2 TO HP3589A
Cl:flfik MARKER1 " Q ' ttx) -v DAC 1000 SPECTRUM/NETWORK
I i ANALYZER
SELECT son INPUT
MUX l l
WRITE CONTROL son 20pF son 20pF
RETIMED J"-"Cl -
CLOCK - CLOCK SLEEP V
OUTPUT' v
'AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.
LE CROY 9210
PULSE GENERATOR
Figure 3. BasicAC Characterization Test Setup
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9761 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. c -5-
A0976]
PIN CONFIGURATION
(MSB) DB9 E . Es] RESET/SLEEP
DB8 E 27 comm
DB7 E E IOUTA
DB6 E E IOUTB
DBS [E 24 ACOM
ADS761
DB4 [E TOP VIEW 23 AVDD
DB3 E (Not to Scale) 22 COMP2
DB2 E Z] FSADJ
DB1 IE E REFIO
(LSB) DBO IE E REFLO
CLOCK IE Es] QOUTB
WRITE E E QOUTA
SELECT E E comps
DVDD IE E DCOM
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 DB9 Most Significant Data Bit (MSB).
2-9 DB8-DBI Data Bits 1-8.
10 DBO Least Significant Data Bit (LSB).
11 CLOCK Clock Input. Both DACs' outputs updated on positive edge of clock and digital filters read respective
mput registers.
12 WRITE Write Input. DAC input registers latched on positive edge of write.
13 SELECT Select Input. Select high routes input data to I DAC; select low routes data to Q DAC.
14 DVDD Digital Supply Voltage (2.7 V to 5.5 V).
15 DCOM Digital Common.
16 COMP3 Internal Bias Node for Switch Driver Circuitry. Decouple t0 ACOM with 0.1 " capacitor.
17 QOUTA Q DAC Current Output. Full-scale current when all data bits are Is.
18 QOUTB Q DAC Complementary Current Output. Full-scale current when all data bits are Os.
19 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
20 REFIO Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V
reference output when internal reference activated. Requires 0.1 pF capacitor to ACOM when internal
reference activated.
21 FSADJ Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.
22 COMP2 Bandwidth/Noise Reduction Node. Add 0.1 pF to AVDD for optimum performance.
23 AVDD Analog Supply Voltage (3V to 5.5 V).
24 ACOM Analog Common.
25 IOUTB I DAC Complementary Current Output. Full-scale current when all data bits are Os.
26 IOUTA I DAC Current Output. Full-scale current when all data bits are Is.
27 COMPl Internal Bias Node for Switch Driver Circuitry. Decouple t0 AGND with 0.1 " capacitor.
28 RESET/SLEEP Power-Down Control Input if Asserted for Four Clock Cycles or Longer. Reset control input if
asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/
SLEEP Mode Operation section.
-6- REV. C
A0976]
DEFINITIONS OF SPECIFICATIONS
Linearity Error
(Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all Os. For IOUTB, 0 mA output is expected when
all inputs are set to ls.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set to
ls minus the output when all inputs are set to OS.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the start
of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in PV-s.
REV. C
Channel Isolation
Channel Isolation is a measure of the level of crosstalk between
channels. It is measured by producing a full-scale 8 MHz signal
output for one channel and measuring the leakage into the other
channel.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth
Total Harmonic Distortion
THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).
Signal-to-Noise and Distortion (SIN+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number
of bits. Using the following formula,
N= (SINAD- 1.76)/6.02
it is possible to get a measure of performance expressed as N, the
effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
Pass Band
Frequency band in which any input applied therein
passes unattenuated to the DAC output.
Stop-Band Rejection
The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.
Group Delay
Number of input clocks between an impulse applied at
the device input and peak DAC output current.
Impulse Response
Response of the device to an impulse applied to the input.
hlMiil-Typieal Performance Characteristics
Typical M Characterization Curves @ 5 ll Supplies
(hllim = 5 ll, DVDD = 5 ll, 5ll n Doubly Terminated Load, TA = 25°C, tum = 40 MSPS, unless otherwise noted, worst of l or ll output
performance shown.)
10dB (Div)
START: 0H2
STOP: 40MHz
TPC f. Single-Tone SFDR (DC
to 2 am, fCLOCK = 2 fDATA)
"us'''):-------- DlFF -6dBFS
DIFF OdBFS _
60 's,
""-......
S/E OdBFS
"ms......,
SIE -cii'psss..-........
0 2.0 4.0 6.0 8.0 10.0
tour (MHz)
"'--..
TPC 4. Out-of-Band SFDR vs.
four (fDATA/Z to 3/2 fonrn)
SFDR © 2.5mA
75 ',',P"
70 NT I, / ISFDR @10mA -
m SFDR lit 5mA
65 ‘SINAD d 2.5mA
SINAD © 5mA
SINAD @ 10mA
60 5 \L
o 2 4 6 s 10
four (MHz)
TPC 7. SiNAD/SFDR VS. IOUTFS
(DC to fonrn/2, Differential Output)
65 10.50
60 "s.----..:''. OdBFo 9.67
" "sstrss. m
% SIE OdBFS """--.c' g
55 DIFF -6dBFS 8.84
1'sss,,.
SIE -6dBFS "'""--a'
50 3.01
0 2.0 4.0 6.0 8.0 10.0
four(MHz)
TPC 2. SINAD (ENOBS) VS.
four (DC to fonm/2)
spun © 40MSPS
75 i i 2,
7o - SFDR © 20MSPS 'iz'f'"""h,
65 / SFDR @1OMSPS
u 55 /
50 // ",,---" l
45 "-"'"'' SINAD @ 40MSPS-
/ SINAD © 20MSPS
40 // SINAD ©10MSPS-
35 I I
-30 -25 -20 -15 -10 -5 -o
AOUT(dBFS)
TPC 5. SINAD vs. Aour (DC to
fonm/2, Differential Output)
SF DR © 5mA
75 l l
SFDR © 10mA>4
70 _-....-"
ts/cu-'''''"
i SFDR © 2.5mA
SINAD © 5mA
SINAD © 2.5mA "
60,,s/w"
'N, SINAD © 10mA
o 2 4 s s 10
tour (MHz)
TPC 8. SINAD/SFDR VS. IOUTFS
(DC to fvnm/2, Single-Ended Output)
DIFF -tidBFS v,,,,/'i'
SIE -6dBFS
(tze---:,',',','' S/E OdBFS
70 V V
DIFF OdBFS
o 5.0 10.0
tour (MHz)
TPC 3. SFDR VS. four (DC to fDATA/Z)
80 I I I
SFDR © 40MSPS
75 D"r's
TO - L, @IZOMSPISZ/r f 'hs,
65 r I
/ SFDR © 10MSPS
'u / /
45 SINAD © 40MSPs
SINAD © 20MSPS
40 w'''" SINAD @ 10MSPS
35 , I l
-30 -25 -20 -15 -10 -5 o
AOUT (dBFS)
TPC 6. SINAD vs. Aour (DC to
foAm/2, Single-Ended Output)
ji" -65
t,' -75
-95 W .,. 'W. l
START: OHz STOP: 20MHz
TPC 9. Wideband Spread-
Spectrum Spectral Plot (DC to fDATA)
REV. C
A0976]
Typical M Characterization Curves @ 3 ll Supplies
(AVIJD = 3 ll, DVDD = 3 ll, 50 n Doubly Terminated Load, T, = 25°C, tum = 10 MSPS, unless otherwise noted, worst of I or il output
performance shown.)
1051303111)
START: ore
P: 10MHa
TPC 10. Single-Tone SFDR (DC to
2 foAm, fcuack = 2 fDATA)
t " DIFIF -m,B,,1s
SIE OdBFS -
-----scr-c::rat:z::
S/E -6dBFS
DIFF OdBFS
0.5 1.0
tour (MHz)
1.5 2.
TPC 13. Out-of-Band SFDR vs.
four (fDATA/2 to 3/2fDATA)
SFDR @ 10mA
L,,cc---sc---;
te5cc'st,-- r
SFDR © 5mA
SFDR @ 2.5mA
SINAD © 2.5mA
SINAD @ 5mA
SINAD © 10mA
2 4 6 8 10
tour (MHz)
TPC 16. SINAD/SFDR vs. IOUTFS
(DC to foAm/2, Differential Output)
REV. C
65 10.50
60 “st 9.67
m "s-s.!,- OdBFS -...----" m
55 - DIFF -6dBFS 8.84
WE -tidBFS
50 8.01
o 0.5 1.0 1.5 2.0 2.5
tour (MHz)
TPC 11. SINAD (ENOBs) vs. four
(DC to fDATA/2)
80 shm © IZOMSP'S _
75 l I [A
SFDR o10MsPs-t' / N
65 //\\
/ SFDR © 40MSPS
m 60 A"
45 // .
',.-'"" SINAD © 40MSPS
/ SINAD © 20MSPS
40 " SINAD © 10MSPS _
-30 -25 -20 -15 -10 -5 o
AOUT (dBFS)
TPC 14. SINAD vs. AOUT (DC to
fopm/2, Differential Output)
SFDR © 5mA ////
" SFDR @10mA r,,,,,,-'''" /
SFDR © 2.5mA 1
SINAD © 5mA
SINAD © 10mA
SINAD © 2.5mA
_,..,......-.....) /
su......---------
o 2 4 6 a 1
tou, (MHz)
TPC 1Z SINAD/SFDR vs. IOUTFS
(DC to fcum/2, Single-Ended Output)
85 l l
"-)ssvs)
80 -SIE -6dBes /
75 \ y /
70 N /
DlFFOdBFS
A _.-....-"
65 f -r-
SIEOdBFS
0 0.5 1.0 1.5 2.0 2.5
tour(MHz)
TPC 12. SFDR VS. four (DC to fDATA/2)
SFDR © 20MSPS
SFDR @ 1ousPs-vtsc, :ts
//\I ))
A" SFDR © 40MSPS -
SINAD © 40MSPS
SINAD © 20MSPS
"''" SINAD © 10MSPS
-3o -25 -2o -15 -10 -5 o
Aour(dBFS)
TPC 15. SINAD vs. AOUT (DC to
am/2, Single-Ended Output)
10:19 (Div)
START: 0H2
STOP: 10MH2
TPC 18. Narrow-Band Spread-
Spectrum Spectral Plot (DC to fDATA)
A0976]
FUNCTIONAL DESCRIPTION
Figure 4 shows a simplified block diagram of the AD9761. The
AD9761 is a complete dual-channel, high speed, 10-bit CMOS
DAC capable of operating up to a 40 MHz clock rate. It has
been optimized for the transmit section of wideband communica-
tion systems employing I and Q modulation schemes. Excellent
matching characteristics between channels reduce the need for
any external calibration circuitry. Dual matching 2X interpola-
tion filters included in the I and Q data path simplify any post
band-limiting filter requirements. The AD9761 interfaces with a
single 10-bit digital input bus that supports interleaved I and Q
input data.
DCOM DVDD CLOCK AOOM AVDD
v V V C
_ LATCH -rs FN -rs , IOUTA
SLEEP I 1/ -v DAC IOUTB
REFERENCE FSADJ
DAC DATA Reno
INPUTS
(10 BITS) BIAS gr,,'',,',
GENERATOR cows
= LATCH -N FN -ts, Q OOUTA
" l 'V ' DAC ooura
WRITE INPUT MUX
SELECT INPUT CONTROL AD9761
Figure 4. Dual DAC Functional Block Diagram
Referring to Figure 4, the AD9761 consists of an analog sec-
tion and a digital section. The analog section includes matched
I and Q 10-bit DACs, a 1.20 V band gap voltage reference, and
a reference control amplifier. The digital section includes two 2X
interpolation filters, segment decoding logic, and some additional
digital input interface circuitry. The analog and digital sections of
the AD9761 have separate power supply inputs (i.e., AVDD and
DVDD) that can operate independently. The digital supply can
operate over a 2.7 V to 5.5 V range, allowing it to accommodate
TTL as well as 3.3 V and 5 V CMOS logic families.The analog
supply must be restricted from 3.0V to 5.5 V to maintain opti-
mum performance.
FUNDAMENTAL15TIMAGE
FREQUENCY DOMAIN
tcuocx fCLocK
FUNDAMENTAL DIGITAL
SUPPRESSED f
OLD CLOCK
1ST IMAGE
Each DAC consists of a large PMOS current source array capable
of providing up to 10 mA of full-scale current, 10mg. Each array is
divided into 15 equal currents that make up the four most signifi-
cant bits (MSBs). The next four bits or middle bits consist of 15
equal current sources whose values are 1/16 of an MSB current
source. The remaining LSBs are binary weighted fractions of
the middle bits' current sources. All of these current sources are
switched to one of two output nodes (i.e., IOUTA or IOUTB)
via PMOS differential current switches.
The full-scale output current, IOUTFS: of each DAC is regulated
from the same voltage reference and control amplifier, thus
ensuring excellent gain matching and drift characteristics
between DACs. IOUTFS can be set from 1 mA to 10 mA via an
external resistor, RSET. The external resistor in combination
with both the reference control amplifier and voltage reference,
VREFIO, sets the reference current, IREF, which is mirrored over
to the segmented current sources with the proper scaling factor.
IOUTFS is exactly 16 times the value of IREF.
The I and Q DACs are simultaneously updated on the rising
edge of CLOCK with digital data from their respective 2X
digital interpolation filters. The 2X interpolation filters essen-
tially multiply the input data rate of each DAC by a factor of
2, relative to its original input data rate, while simultaneously
reducing the magnitude of the first image associated with the
DAC's original input data rate. Since the AD9761 supports a
single 10-bit digital bus with interleaved I and Q input data, the
original I and Q input data rate before interpolation is one-half
the CLOCK rate. After interpolation, the data rate into each I
and Q DAC becomes equal to the CLOCK rate.
The benefits of an interpolation filter are illustrated in Figure 5,
which shows an example of the frequency and time domain rep-
resentation of a discrete time sine wave signal before and after
it is applied to a digital interpolation filter. Images of the sine
wave signal appear around multiples of the DAC's input data
rate as predicted by the sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modified by the DAC's sin(x)/(x) response. In many
band-limited applications, these images must be suppressed by
an analog filter following the DAC. The complexity of this ana-
l /FILTER
fCLOCK fCLOCK
fCLOCK
INPUT DATA LATCH
2x INTEFtPOLATl0N FILTER
2 xi N
ICLOCK
tCLOCK
Figure 5. Time and Frequency Domain Example of Digital Interpolation Filter
-10- REV. C
A0976]
log filter is typically determined by the proximity of the desired
fundamental to the first image and the required amount of image
suppression.
Referring to Figure 5, the "new" first image associated with the
DAC's higher data rate after interpolation is "pushed" out fur-
ther relative to the input signal. The "old" first image associated
with the lower DAC data rate before interpolation is suppressed
by the digital filter. As a result, the transition band for the analog
reconstruction filter is increased, thus reducing the complexity
of the analog filter.
The digital interpolation filters for I and Q paths are identi-
cal 43-tap half-band symmetric FIR filters. Each filter receives
de-interleaved I or Q data from the digital input interface.The
input CLOCK signal is internally divided by 2 to generate the
filter clock. The filters are implemented with two parallel paths
running at the filter clock rate. The output from each path is
selected on opposite phases of the filter clock, thus producing
interpolated filtered output data at the input clock rate. The
frequency response and impulse response of these filters are
shown in Figures 2a and 2b. Table I lists the idealized filter
coefficients that correspond to the filter's impulse response.
The digital section of the AD9761 also includes an input interface
section designed to support interleaved I and Q input data from
a single 10-bit bus. This section de-interleaves the I and Q input
data while ensuring its proper pairing for the 2X interpolation
filters. A RESET/SLEEP input serves a dual function by providing
a reset function for this section as well as providing power-down
functionality. Refer to the Digital Inputs and Interleaved Interface
Considerations and RESET/SLEEP Mode Operation sections for
a more detailed discussion.
DAC TRANSFER FUNCTION
Each I and Q DAC provides complementary current output
pins: IOUT(A/B) and QOUT(A/B), respectively. Note that
QOUTA and QOUTB operate identically to IOUTA and
IOUTB. IOUTA will provide a near full-scale current output,
Iourrs, when all bits are high (i.e., DAC CODE = 1023), while
IOUTB, the complementary output, provides no current.The
current outputs of IOUTA and IOUTB are a function of both
the input code and IOUTFS and can be expressed as
10m = (DAC CODE/1024) 8 1oures (1)
IOUTB = (1023 - DAC CODE) /1024 X loans (2)
where:
DAC CODE = 0 to 1023 (i.e., decimal representation).
As previously mentioned, IOUTFS is a function of the reference
current, I REF, which is nominally set by a reference, VREHO, and
external resistor, Rser. It can be expressed as
IOUTFS = 16 X IREF (3)
where:
IREF = VREFIO /RSET (4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, which are tied to analog common, ACOM. Note
that RLOAD represents the equivalent load resistance seen by
REV. C
IOUTA or IOUTB.The single-ended voltage output appearing
at IOUTA and IOUTB pins is simply
VIOLITA = IOUTA XRLOAD (5)
VIOUTB = IOUTB M RLOAD (6)
Note that the full-scale value of VIOUTA and VIOUTB should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, VIDIFF, appearing across IOUTA and
IOUTB is
VIDIFF = (IIOUTA - IIOUTB) M RLOAD (7)
Substituting the values of 110%.], I IOUTB, and I REF, VIDIFF can be
expressed as
VMF = (p DAC CODE _1023)/1024)}><
(16 RLOAD /RSET) X VREFIO (8)
These last two equations highlight some of the advantages of
operating the AD9761 differentially. First, differential opera-
tion will help cancel common-mode error sources associated
with IIOUTA and IIOUTB, such as noise and distortion. Second,
the differential code-dependent current and subsequent volt-
age, VIDIFF, is twice the value of the single-ended voltage output
(i.e., VIOUTA or VIOUTB), thus providing twice the signal power to
the load.
REFERENCE OPERATION
The AD9761 contains an internal 1.20 V band gap reference that
can be easily disabled and overridden by an external reference.
REFIO serves as either an input or output depending on whether
the internal or an external reference is selected. If REFLO is tied
to ACOM as shown in Figure 6, the internal reference is activated
and REFIO provides a 1.20 V output. In this case, the internal ref-
erence must be filtered externally with a ceramic chip capacitor of
0.1 " or greater from REFIO t0 REFLO. Also, REFIO should be
buffered with an external amplifier having a low input bias current
(i.e., <1 pA) if any additional loading is required.
OPTIONAL EXTERNAL
REF BUFFER FOR
ADD'T'OyAL LOADS REFLO COMP2 AVDD
i CURRENT
$0.1};F FSADJ SOURCE
/ RSET
COMPENSATION 2kn
CAPACITOR
REQUIRED
AD9761
Figure 6. Internal Reference Configuration
The internal reference can also be disabled by connecting
REFLO to AVDD. In this case, an external reference may then
be applied to REFIO as shown in Figure 7.The external reference
may provide either a fixed reference voltage to enhance accura-
cy and drift performance or a varying reference voltage for gain
control. Note that the 0.1 WF compensation capacitor is not
required since the internal reference is disabled and the high
input impedance (i.e., 1 Mn) of REFIO minimizes any loading
of the external reference.
