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AD9751ASTADIN/a4avai10-Bit, 300 MSPS High Speed TxDAC+® D/A Converter


AD9751AST ,10-Bit, 300 MSPS High Speed TxDAC+® D/A ConverterSPECIFICATIONS Transformer-Coupled Output, 50  Doubly Terminated, unless otherwise noted.)Paramete ..
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AD9751AST
10-Bit, 300 MSPS High Speed TxDAC+® D/A Converter
REV. C
10-Bit, 300MSPS
High Speed TxDAC+ D/A Converter
FUNCTIONAL BLOCK DIAGRAM
AVDDACOM
REFIO
FSADJ
PORT1IOUTA
IOUTB
DVDDDCOM
CLK+
CLK–
CLKVDD
PLLVDD
CLKCOM
RESET LPF DIV0 DIV1 PLLLOCK
PORT2
PRODUCT DESCRIPTION

The AD9751 is a dual muxed port, ultrahigh speed, single-
channel, 10-bit CMOS DAC. It integrates a high quality 10-bit
TxDAC+ core, a voltage reference, and digital interface circuitry
into a small 48-lead LQFP package. The AD9751 offers excep-
tional ac and dc performance while supporting update rates up
to 300MSPS.
The AD9751 has been optimized for ultrahigh speed applica-
tions up to 300 MSPS where data rates exceed those possible on
a single data interface port DAC. The digital interface consists
of two buffered latches as well as control logic. These latches
can be time multiplexed to the high speed DAC in several ways.
This PLL drives the DAC latch at twice the speed of the exter-
nally applied clock and is able to interleave the data from the
two input channels. The resulting output data rate is twice that
of the two input channels. With the PLL disabled, an external
2× clock may be supplied and divided by two internally.
The CLK inputs (CLK+/CLK–) can be driven either differen-
tially or single-ended, with a signal swing as low as 1 V p-p.
FEATURES
10-Bit Dual Muxed Port DAC
300 MSPS Output Update Rate
Excellent SFDR and IMD Performance
SFDR to Nyquist @ 25 MHz Output: 64 dB
Internal Clock Doubling PLL
Differential or Single-Ended Clock Input
On-Chip 1.2 V Reference
Single 3.3 V Supply Operation
Power Dissipation: 155mW @ 3.3 V
48-Lead LQFP
APPLICATIONS
Communications: LMDS, LMCS, MMDS
Base Stations
Digital Synthesis
QAM and OFDM

The DAC utilizes a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and maximize dynamic accuracy. Differential current
outputs support single-ended or differential applications. The
differential outputs each provide a nominal full-scale current
from 2mA to 20 mA.
The AD9751 is manufactured on an advanced low cost 0.35µm
CMOS process. It operates from a single supply of 3.0 V to 3.6V
and consumes 155 mW of power.
PRODUCT HIGHLIGHTS
The AD9751 is a member of a pin compatible family of high
speed TxDAC+s, providing 10-, 12-, and 14-bit resolution.Ultrahigh Speed 300 MSPS Conversion Rate.Dual 10-Bit Latched, Multiplexed Input Ports. The AD9751
features a flexible digital interface allowing high speed data
conversion through either a single or dual port input.Low Power. Complete CMOS DAC function operates on
155 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation.On-Chip Voltage Reference. The AD9751 includes a 1.20V
temperature compensated band gap voltage reference.
*. Patent numbers 5450084, 5568145, 5689257, and 5703519.
Other patents pending.
AD9751–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)

TEMPERATURE COEFFICIENTS
NOTESMeasured at IOUTA, driving a virtual ground.Nominal full-scale current, IOUTFS, is 32× the IREF current.An external buffer amplifier is recommended to drive any external load.100 MSPS fDAC with PLL on, fOUT = 1 MHz, all supplies = 3.0 V.300 MSPS fDAC.±5% power supply variation.
Specifications subject to change without notice.
AD9751
DYNAMIC SPECIFICATIONS

NOTESMeasured single-ended into 50 Ω load.Single-Port Mode (PLL disabled, DIV0 = 1, DIV1 = 0, data on Port 1).
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = CLKVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, Differential
Transformer-Coupled Output, 50 � Doubly Terminated, unless otherwise noted.)
AD9751
DIGITAL SPECIFICATIONS(TMIN to TMAX, AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)

CLK INPUTS
*Min CLK Frequency applies only when using internal PLL. When PLL is disabled, there is no minimum CLK frequency.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9751 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
THERMAL CHARACTERISTIC
Thermal Resistance

θJA = 91°C/W
Figure 1.I/O Timing
ABSOLUTE MAXIMUM RATINGS*

Digital Data Inputs (DB9 to DB0)
CLK+/CLK–, PLLLOCK
DIV0, DIV1, RESET
LPF
Junction Temperature
Storage Temperature
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
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