AD9696 ,Ultrafast TTL ComparatorsCHARACTERISTICS unless otherwise noted) 08C to +708C –558C to +1258C AD9696/AD9698 ..
AD9696KN ,Ultrafast TTL ComparatorsAPPLICATIONS1 μA. A latch enable input is provided to allow operation in ei-High Speed Line Receive ..
AD9696KN ,Ultrafast TTL Comparatorsapplications.Peak DetectorsWindow ComparatorsThe AD9696 and AD9698 are both available as commercial ..
AD9696KQ ,Ultrafast TTL Comparatorsapplications asATE, communications receivers and test instruments.FUNCTIONAL BLOCK DIAGRAMAD9696AD9 ..
AD9696KR ,Ultrafast TTL ComparatorsSPECIFICATIONS1 2ABSOLUTE MAXIMUM RATINGS Operating Temperature RangeSupply Voltage (+V /–V ) . . . ..
AD9696TQ ,Ultrafast TTL ComparatorsSPECIFICATIONS1 2ABSOLUTE MAXIMUM RATINGS Operating Temperature RangeSupply Voltage (+V /–V ) . . . ..
ADS826EG4 ,10-Bit, 60 MSPS ADC SE/Diff, Int/Ext Ref., program. input range w/Pwrdn and comp. to ADS822/3/5/8 28-SSOP -40 to 85ELECTRICAL CHARACTERISTICSAt T = full specified temperature range, V = +5V single-ended input range ..
ADS8284 ,18 bit, 1 MSPS, 4 channel, Pseudo bipolar, differential ADC with onboard ADC driver OPA 64-VQFN -40 to 85Maximum Ratings . 68.1 Application Information........ 336.2 Handling Ratings. 68.2 Typical Applica ..
ADS8284IBRGCR ,18 bit, 1 MSPS, 4 channel, Pseudo bipolar, differential ADC with onboard ADC driver OPA 64-VQFN -40 to 85Electrical Characteristics....... 710.1 Trademarks..... 376.6 Timing Requirements, 5 V.. 1010.2 Ele ..
ADS8284IBRGCT ,18 bit, 1 MSPS, 4 channel, Pseudo bipolar, differential ADC with onboard ADC driver OPA 64-VQFN -40 to 85 SLAS628A–MARCH 2009–REVISED APRIL 2014Device Comparison TableTYPE/SPEED 500 kHz ~600 kHz 750 kHz 1 ..
ADS8284IRGCT ,18 bit, 1 MSPS, 4 channel, Pseudo bipolar, differential ADC with onboard ADC driver OPA 64-VQFN -40 to 85Features 3 DescriptionThe ADS8284 is a high-performance analog system-1• 1.0-MHz Sample Rate, Zero ..
ADS828E ,10-Bit/ 75MHz Sampling ANALOG-TO-DIGITAL CONVERTERMAXIMUM RATINGSELECTROSTATIC+V .... +6VSDISCHARGE SENSITIVITYAnalog Input ....... –0.3V to (+V + 0. ..
AD9696-AD9696KN-AD9696KQ-AD9696KR-AD9696TQ-AD9698-AD9698KN
Ultrafast TTL Comparators
REV.B
Ultrafast
TTL Comparators
FEATURES
4.5 ns Propagation Delay
200 ps Maximum Propagation Delay Dispersion
Single +5 V or 65 V Supply Operation
Complementary Matched TTL Outputs
APPLICATIONS
High Speed Line Receivers
Peak Detectors
Window Comparators
High Speed Triggers
Ultrafast Pulse Width DiscriminatorsBoth devices allow the use of either a single +5 V supply or
±5 V supplies. The choice of supplies determines the common
mode input voltage range available: –2.2 V to +3.7 V for ±5 V
operation, +1.4 V to +3.7 V for single +5 V supply operation.
The differential input stage features high precision, with offset
voltages that are less than 2 mV and offset currents less than
1 μA. A latch enable input is provided to allow operation in ei-
ther sample-and-hold or track-and-hold applications.
The AD9696 and AD9698 are both available as commercial
temperature range devices operating from ambient temperatures
of 0°C to +70°C, and as extended temperature range devices for
ambient temperatures from –55°C to +125°C. Both versions are
available qualified to MIL-STD-883 class B.
Package options for the AD9696 include a 10-pin TO-100 metal
can, an 8-pin ceramic DIP, an 8-pin plastic DIP, and an 8-lead
small outline plastic package. The AD9698 is available in a
16-pin ceramic DIP, a 16-lead ceramic gullwing, a 16-pin plastic
DIP and a 16-lead small outline plastic package. Military quali-
fied versions of the AD9696 come in the TO-100 can and
ceramic DIP; the dual AD9698 comes in ceramic DIP.
GENERAL DESCRIPTIONThe AD9696 and AD9698 are ultrafast TTL-compatible volt-
age comparators able to achieve propagation delays previously
possible only in high performance ECL devices. The AD9696 is
a single comparator providing 4.5 ns propagation delay, 200 ps
maximum delay dispersion and 1.7 ns setup time. The AD9698
is a dual comparator with equally high performance; both de-
vices are ideal for critical timing circuits in such applications as
ATE, communications receivers and test instruments.
FUNCTIONAL BLOCK DIAGRAM
AD9696/AD9698 Architecture
AD9698
AD9696
NONINVERTING
INPUT
INVERTING
INPUT
LATCH
ENABLE
Q OUTPUT
Q OUTPUT
NONINVERTING
INPUT
INVERTING
INPUT
LATCH
ENABLE
Q OUTPUT
Q OUTPUT
NONINVERTING
INPUT
INVERTING
INPUT
LATCH
ENABLE
Q OUTPUT
Q OUTPUT
AD9696/AD9698–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1Supply Voltage (+VS/–VS) . . . . . . . . . . . . . . . . . . . .+7 V/–7 V
Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .±5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .5.4 V
Latch Enable Voltage . . . . . . . . . . . . . . . . . . . . .–0.5 V to +VS
Output Current (Continuous) . . . . . . . . . . . . . . . . . . .20 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .600 mW
Operating Temperature Range2
AD9696/AD9698KN/KQ/KR . . . . . . . . . . . .0°C to +70°C
AD9696/AD9698TQ . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature
KQ/TQ Suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
KN/KR Suffixes . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . .+300°C
ELECTRICAL CHARACTERISTICS
(Supply Voltages = –5.2 V and +5.0 V; load as specified in Note 4,
unless otherwise noted)LATCH ENABLE INPUT
DIGITAL OUTPUTS
SWITCHING PERFORMANCE
NOTESAbsolute maximum ratings are limiting values, to be applied individually,
and beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Typical thermal impedances:
AD9696 Metal CanθJA = 170°C/WθJC = 50°C/W
AD9696 Ceramic DIPθJA = 110°C/WθJC = 20°C/W
AD9696 Plastic DIPθJA = 160°C/WθJC = 30°C/W
AD9696 Plastic SOICθJA = 180°C/WθJC = 30°C/W
AD9698 Ceramic DIPθJA = 90°C/WθJC = 25°C/W
AD9698 Plastic DIPθJA = 100°C/WθJC = 20°C/W
AD9698 Plastic SOICθJA = 120°C/WθJC = 20°C/WLoad circuit has 420 Ω from +VS to output; 460 Ω from output to ground.RS ≤100 Ω.Propagation delays measured with 100 mV pulse; 10 mV overdrive.Supply voltages should remain stable within ±5% for normal operation.Specification applies to both +5 V and ±5 V supply operation.Specification applies to only ±5 V supply operation.Measured with nominal values ±5% of +VS and –VS.Although fall time is faster than rise time, the complementary outputs cross at
midpoint of logic swing because of delay on start of falling edge.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C, and sample tested at
specified temperatures.
III–Sample tested only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C.
100% production tested at temperature extremes for
extended temperature devices; sample tested at temp-
erature extremes for commercial/industrial devices.
ORDERING GUIDENOTESN = Plastic DIP, Q = Cerdip, R = Small Outline (SOIC), Z = Ceramic Leaded
Chip Carrier.Refer to AD9696TZ/883B military data sheet.Refer to AD9698TZ/883B military data sheet.
AD9696/AD9698
AD9696/AD9698
PIN CONFIGURATIONS
AD9696KN/KR/KQ/TQ/TZ
Q1OUT (N/C)
Q1OUT (–VS)
GROUND (–IN1)
LATCH ENABLE 1 (+IN1)
N/C (+IN2)
–VS (–IN2)
–IN1 (+VS)9
+IN1 (N/C)+IN2 (LATCH ENABLE 2)
–IN2 (GROUND)
N/C (Q2OUT)
LATCH ENABLE 2 (Q1OUT)
Q2OUT (GROUND)
Q2OUT (LATCH ENABLE 1)
AD9698KN/KQ/TQ
[AD9698KR/TZ PINOUTS SHOWN IN ( )]
GROUND (Q1OUT)
+VS (Q2OUT)
LATCH
ENABLE+VS
+IN
–IN
–VS
GROUND
QOUT
QOUTGROUND
LATCH
ENABLE 1
N/C
–VS
–IN1
+IN1
+IN2
–IN2
+VS
LATCH
ENABLE 2
Q2OUT
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9696/AD9698 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
LATCH
ENABLE
DIFFERENTIAL
INPUT VOLTAGE
– MINIMUM SETUP TIME (Typically 1.7ns)
– MINIMUM HOLD TIME (Typically 1.9ns)
– INPUT TO OUTPUT DELAY
– LATCH ENABLE TO OUTPUT DELAY
tPD
tPD (E)
– MINIMUM LATCH ENABLE PULSE WIDTH (Typically 2.5ns)
– INPUT OFFSET VOLTAGE
– OVERDRIVE VOLTAGE
VOS
VODPW (E)tSAD9696/AD9698 Timing Diagram
DIE LAYOUT AND MECHANICAL INFORMATIONDie Dimensions AD9696 . . . . . . . . . . . . .59×71×15 (±2) mils
AD9698 . . . . . . . . . . . .79×109×15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4×4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Nitride
THEORY OF OPERATIONRefer to the block diagram of the AD9696/AD9698 compara-
tors. The AD9696 and AD9698 TTL voltage comparator archi-
tecture consists of five basic stages: input, latch, gain, level shift
and output. Each stage is designed to provide optimal perfor-
mance and make it easy to use the comparators.
The input stage operates with either a single +5-volt supply, or
with a +5-volt supply and a –5.2-volt supply. For optimum
power efficiency, the remaining stages operate with only a single
+5-volt supply. The input stage is an input differential pair
without the customary emitter follower buffers. This configura-
tion increases input bias currents but maximizes the input volt-
age range.
A latch stage allows the most recent output state to be retained
as long as the latch input is held high. In this way, the input to
the comparator can be changed without any change in the out-
put state. As soon as the latch enable input is switched to LOW,
the output changes to the new value dictated by the signal ap-
plied to the input stage.
The gain stage assures that even with small values of input volt-
age, there will be sufficient levels applied to the following stages
to cause the output to switch TTL states as required. A level
shift stage between the gain stage and the TTL output stage
guarantees that appropriate voltage levels are applied from the
gain stage to the TTL output stage.
Only the output stage uses TTL logic levels; this minimum use
of TTL circuits maximizes speed and minimizes power con-
sumption. The outputs are clamped with Schottky diodes to as-
sure that the rising and falling edges of the output signal are
closely matched.
The AD9696 and AD9698 represent the state of the art in high
speed TTL voltage comparators. Great care has been taken to
optimize the propagation delay dispersion performance. This as-
AD9696/AD9698 R1 + R2 >5kΩ
A1 ,A2 = AD708 or OP– 290
(±5V) (+5V)
Q1 OUT
+Q2 OUTFigure 1. AD9698 Used as Window Detector
When configured as shown, the op amps generate reference lev-
els for the comparators that are equally spaced above and below
the applied VIN. The width of the window is established by the
ratio of R1 and R2. For a given ratio of R1 and R2, +VREF and
–VREF will be fixed percentages above and below VIN. As an ex-
ample, using 2.2 kΩ for R1 and 10 kΩ for R2 creates a ±10%
window. When VIN equals +3 V, +VREF will be +3.3 V and
–VREF will be +2.7 V. Likewise, for a –2 V input, the thresholds
will be –1.8 V and –2.2 V. Windows of differing percentage
width can be calculated with the equation:
(1–X)/2X = R2/R1
where:
X = % window
Additionally, the low impedance of the op amp outputs assures
that the threshold voltages will remain constant when the input
currents change as the signal passes through the threshold volt-
age levels.
The output of the AND gate will be high while the signal is in-
side the window. Q1OUT will be high when the signal is above
+VREF, and Q2OUT will be high when the signal is below –VREF.
Crystal OscillatorOscillators are used in a wide variety of applications from audio
circuits to waveform generators, from ATE triggers and tele-
communications transceivers to radar. Figure 2 shows a versatile
and inexpensive oscillator. The circuit uses the AD9696, in a
positive feedback mode, and is capable of generating accurate
and stable oscillations with frequencies ranging from 1 MHz to
more than 40 MHz.
To generate oscillations from 1 to 25 MHz, a fundamental
mode crystal is used without the dc blocking capacitor and
choke. The parallel capacitor on the inverting input is selected
for stability (0.1 μF for 1–10 MHz; 220 pF for frequencies
above 10 MHz).
APPLICATIONS
GeneralTwo characteristics of the AD9696 and AD9698 should be con-
sidered for any application. First is the fact that all TTL com-
parators are prone to oscillate if the inputs are close to equal for
any appreciable period of time. One instance of this happening
would be slow changes in the unknown signal; the probability of
oscillation is reduced when the unknown signal passes through
the threshold at a high slew rate. Another instance is if the un-
known signal does not overdrive the comparator logic. Unless
they are overdriven, TTL comparators have undershoot when
switching logic states. The smaller the overdrive, the greater the
undershoot; when small enough, the comparator will oscillate,
not being able to determine a valid logic state. For the AD9696
and AD9698, 20 mV is the smallest overdrive which will assure
crisp switching of logic states without significant undershoot.
The second characteristic to keep in mind when designing
threshold circuits for these comparators is twofold: (1) bias cur-
rents change when the threshold is exceeded; and (2) ac input
impedance decreases when the comparator is in its linear region.
During the time both transistors in the differential pair are con-
ducting, the ac input impedance drops by orders of magnitude.
Additionally, the input bias current switches from one input to
the other, depending upon whether or not the threshold is ex-
ceeded. As a result, the input currents follow approximately the
characteristic curves shown below.
SIGNAL
VOLTAGE
AT +INPUT
+INPUT
CURRENT
– INPUT
CURRENT
LINEAR
REGIONThreshold Input Currents
This characteristic will not cause problems unless a high imped-
ance threshold circuit or drive circuit is employed. A circuit
similar to that shown in the window comparator application can
eliminate this possible problem.
Window ComparatorMany applications require determining when a signal’s voltage
falls within, above, or below a particular voltage range. A simple
tracking window comparator can provide this data. Figure 1
shows such a window comparator featuring high speed, TTL
compatibility, and ease of implementation.
Two comparators are required to establish a “window” with up-
per and lower threshold voltages. The circuit shown uses the
AD9698 dual ultrafast TTL comparator. In addition to the cost
and space savings over a design using two single comparators,
the dual comparator on a single die produces better matching of
both dc and dynamic characteristics.
