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AD9235BCP-65 |AD9235BCP65ADN/a2avai12-Bit, 20/40/65 MSPS 3 V A/D Converter
AD9235BRU-20 |AD9235BRU20ADN/a1avai12-Bit, 20/40/65 MSPS 3 V A/D Converter


AD9235BCP-65 ,12-Bit, 20/40/65 MSPS 3 V A/D ConverterSPECIFICATIONS 1.0 V internal reference, T to T , unless otherwise noted.)MIN MAXTest AD9235BRU-20 ..
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AD9235BRUZ-20 , 12-Bit, 20/40/65 MSPS 3 V A/D Converter
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AD9235BCP-65-AD9235BRU-20
12-Bit, 20/40/65 MSPS 3 V A/D Converter
REV. B
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single 3 V Supply Operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low Power: 300 mW at 65 MSPS
Differential Input with 500 MHz Bandwidth
On-Chip Reference and SHA
DNL = �0.4 LSB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
IS-95, CDMA-One, IMT-2000
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
PRODUCT DESCRIPTION

The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters. This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9235 uses a multistage differential
pipelined architecture with output error correction logic to provide
12-bit accuracy at 20/40/65 MSPS data rates and guarantee
no missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
analog-to-digital converters, the AD9235 is suitable for applica-
tions in communications, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance. The digital output data is presented
in straight binary or twos complement formats. An out-of-range
(OTR) signal indicates an overflow condition that can be used
with the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9235 is available
in a 28-lead thin shrink small outline package (TSSOP) and a
32-lead chip scale package (LFCSP) and is specified over the
industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS

1. The AD9235 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate
2.5 V and 3.3 V logic families.
2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
3. The patented SHA input maintains excellent performance
for input frequencies up to 100 MHz and can be configured
for single-ended or differential operation.
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulsewidths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
12-Bit, 20/40/65 MSPS
3 V A/D Converter
AD9235–SPECIFICATIONS
DC SPECIFICATIONS

INTERNAL VOLTAGE
REFERENCE
REFERENCE INPUT
NOTESGain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2 for the equivalent analog input structure.Measured with dc input at maximum clock rate.Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input,
1.0 V internal reference, TMIN to TMAX, unless otherwise noted.)
AD9235
DRVDD = 2.5 V
*Output voltage levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS

NOTES
1For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
AD9235–SPECIFICATIONS
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input, AIN = –0.5 dBFS,
1.0 V internal reference, TMIN to TMAX, unless otherwise noted.)AC SPECIFICATIONS

SIGNAL-TO-NOISE RATIO
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
NOTESAbsolute maximum ratings are limiting values to be applied individually and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Typical thermal impedances (28-lead TSSOP), θJA = 67.7°C/W; (32-lead LFCSP),
θJA = 32.5°C/W, θJC = 32.71°C/W. These measurements were taken on a 4-layer
board in still air, in accordance with EIA/JESD51-1.
EXPLANATION OF TEST LEVELS
100% production tested.100% production tested at 25°C and sample tested at
specified temperatures.
IIISample tested only.Parameter is guaranteed by design and characterization testing.Parameter is a typical value only.100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for military
devices.
ORDERING GUIDE

*It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of
the package is achieved with exposed paddle soldered to the customer board.
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
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