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AD9226ARSADN/a34avaiComplete 12-Bit, 65 MSPS ADC Converter
AD9226ARSANALOGN/a12avaiComplete 12-Bit, 65 MSPS ADC Converter
AD9226ASTADN/a241avaiComplete 12-Bit, 65 MSPS ADC Converter


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AD9226ARS-AD9226AST
Complete 12-Bit, 65 MSPS ADC Converter
REV.0
Complete 12-Bit, 65 MSPS
ADC Converter
FUNCTIONAL BLOCK DIAGRAM
VINA
CAPT
CAPB
SENSE
OTR
BIT 1
(MSB)
BIT 12
(LSB)
VREF
DRVSSAVSS
VINB
REFCOM
DRVDDAVDDCLK
MODE
FEATURES
Signal-to-Noise Ratio: 69 dB @ fIN = 31 MHz
Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHz
Intermodulation Distortion of –75 dBFS @ fIN = 140 MHz
ENOB = 11.1 @ fIN = 10 MHz
Low-Power Dissipation: 475 mW
No Missing Codes Guaranteed
Differential Nonlinearity Error: �0.6 LSB
Integral Nonlinearity Error: �0.6 LSB
Clock Duty Cycle Stabilizer
Patented On-Chip Sample-and-Hold with
Full Power Bandwidth of 750 MHz
Straight Binary or Two’s Complement Output Data
28-Lead SSOP, 48-Lead LQFP
Single 5 V Analog Supply, 3 V/5 V Driver Supply
Pin-Compatible to AD9220, AD9221, AD9223,
AD9224, AD9225
PRODUCT DESCRIPTION

The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS
analog-to-digital converter with an on-chip, high-performance
sample-and-hold amplifier and voltage reference. The AD9226
uses a multistage differential pipelined architecture with a pat-
ented input stage and output error correction logic to provide
12-bit accuracy at 65 MSPS data rates. There are no missing
codes over the full operating temperature range (guaranteed).
The input of the AD9226 allows for easy interfacing to both
imaging and communications systems. With a truly differential
input structure, the user can select a variety of input ranges and
offsets including single-ended applications.
The sample-and-hold amplifier (SHA) is well suited for IF
undersampling schemes such as in single-channel communi-
cation applications with input frequencies up to and well
beyond Nyquist frequencies.
The AD9226 has an on-board programmable reference. For sys-
tem design flexibility, an external reference can also be chosen.
A single clock input is used to control all internal conversion
cycles. An out-of-range signal indicates an overflow condition
that can be used with the most significant bit to determine low
or high overflow.
The AD9226 has two important mode functions. One will set
the data format to binary or two’s complement. The second will
make the ADC immune to clock duty cycle variations.
PRODUCT HIGHLIGHTS
IF Sampling—The patented SHA input can be configured for

either single-ended or differential inputs. It will maintain out-
standing AC performance up to input frequencies of 300 MHz.
Low Power—The AD9226 at 475 mW consumes a fraction of

the power presently available in existing, high-speed monolithic
solutions.
Out of Range (OTR)—The OTR output bit indicates when

the input signal is beyond the AD9226’s input range.
Single Supply—The AD9226 uses a single 5 V power supply

simplifying system power supply design. It also features a sepa-
rate digital output driver supply line to accommodate 3V andV logic families.
Pin Compatibility—The AD9226 is similar to the AD9220,

AD9221, AD9223, AD9224, and AD9225 ADCs.
Clock Duty Cycle Stabilizer—Makes conversion immune to

varying clock pulsewidths.
AD9226–SPECIFICATIONS
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, Differential inputs, TMIN to TMAX unless otherwise
noted.)DC SPECIFICATIONS

NOTESIncludes internal voltage reference error.Excludes internal voltage reference error.Load regulation with 1 mA load current (in addition to that required by the AD9226).
AD9226
DIGITAL SPECIFICATIONS

LOGIC OUTPUTS (With DRVDD = 3 V)
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS

CLOCK Pulsewidth High
CLOCK Pulsewidth Low
Output Delay
Pipeline Delay (Latency)
NOTES
1The clock period may be extended to 10 µs without degradation in specified performance @ 25°C.When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.LQFP package.
Specifications subject to change without notice.
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)
(TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)
n+1n+2n+6
n+8nANALOG
INPUT
CLOCK
DATA
OUT
AD9226–SPECIFICATIONS
AC SPECIFICATIONS(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted.)

NOTES1.0 V Reference and Input Span
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9226 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1

NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
2LQFP package.
THERMAL RESISTANCE

θJC SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23°C/W
θJA SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.3°C/W
θJC LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17°C/W
θJA LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76.2°C/W
EXPLANATION OF TEST LEVELS
Test Level
100% production tested.
II.100% production tested at 25°C and sample tested at
specified temperatures. AC testing done on sample basis.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
VI.All devices are 100% production tested at 25°C; sample tested
at temperature extremes.
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