AD9042AD-AD9042AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD9042AD ,12-Bit, 41 MSPS Monolithic A/D ConverterAPPLICATIONSTIMINGENCODE MSB LSBCellular/PCS Base StationsGPS Anti-Jamming ReceiversGNDD11 D10 D9 D ..
AD9042AST ,12-Bit, 41 MSPS Monolithic A/D ConverterSPECIFICATIONS AD9042V tied to V through 50 Ω; T = –408C, T = +858C)REF OFFSET MIN MAXTest AD9042AS ..
AD9048JJ ,Monolithic 8-Bit Video A/D Converterspecifications.Devices operating over two ambient temperature ranges andwith two grades of linearit ..
AD9048JQ ,Monolithic 8-Bit Video A/D ConverterSPECIFICATIONS1ABSOLUTE MAXIMUM RATINGS5Output Short-Circuit Duration . . . . . . . . . . . . . . . ..
AD9048KJ ,Monolithic 8-Bit Video A/D ConverterFEATURES35 MSPS Encode Rate16 pF Input CapacitanceNLINV 12AD9048550 mW Power Dissipation NMINV 28V ..
AD9048KQ ,Monolithic 8-Bit Video A/D ConverterAPPLICATIONS 2 1 D1 (MSB)EProfessional Video SystemsNR 2 D2CSpecial Effects GeneratorsO3D3127DElect ..
ADS5481IRGCT ,16-bit 80MSPS ADC With Buffered Analog Input 64-VQFN -40 to 85FEATURES APPLICATIONS• Wireless Infrastructure (Multi-Carrier GSM,23• 80/105/135-MSPS Sample RatesW ..
ADS5481IRGCT ,16-bit 80MSPS ADC With Buffered Analog Input 64-VQFN -40 to 85MAXIMUM RATINGSOver operating free-air temperature range, unless otherwise noted.ADS5481, ADS5482, ..
ADS5482IRGCT ,16-bit, 105MSPS High Speed ADCs 64-VQFN -40 to 85FEATURES APPLICATIONS• Wireless Infrastructure (Multi-Carrier GSM,23• 80/105/135-MSPS Sample RatesW ..
ADS5483IRGCR , 16-Bit, 80/105/135-MSPS Analog-to-Digital Converters
ADS5483IRGCT ,16-bit 135MSPS ADC with buffered inputs 64-VQFN -40 to 85FEATURES APPLICATIONS• Wireless Infrastructure (Multi-Carrier GSM,23• 80/105/135-MSPS Sample RatesW ..
ADS5484IRGCR , 16-Bit, 170/200-MSPS Analog-to-Digital Converters

AD9042AD-AD9042AST
12-Bit, 41 MSPS Monolithic A/D Converter
REV.A12-Bit, 41 MSPS
Monolithic A/D Converter
FEATURES
41 MSPS Minimum Sample Rate
80 dB Spurious-Free Dynamic Range
595 mW Power Dissipation
Single +5 V Supply
On-Chip T/H and Reference
Twos Complement Output Format
CMOS-Compatible Output Levels
APPLICATIONS
Cellular/PCS Base Stations
GPS Anti-Jamming Receivers
Communications Receivers
Spectrum Analyzers
Electro-Optics
Medical Imaging
ATE
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTION
The AD9042 is a high speed, high performance, low power,
monolithic 12-bit analog-to-digital converter. All necessary
functions, including track-and-hold (T/H) and reference are
included on chip to provide a complete conversion solution.
The AD9042 runs off of a single +5V supply and provides
CMOS-compatible digital outputs at 41MSPS.
Designed specifically to address the needs of wideband,
multichannel receivers, the AD9042 maintains 80 dB
spurious-free dynamic range (SFDR) over a bandwidth ofMHz. Noise performance is also exceptional; typical
signal-to-noise ratio is 68dB.
The AD9042 is built on Analog Devices’ high speed complemen-
tary bipolar process (XFCB) and uses an innovative multipass
architecture. Units are packaged in a 28-pin DIP; this custom
AD9042AD PIN DESIGNATIONS
NC = NO CONNECT
GND
DVCC
GND
ENCODEENCODE
GND
GND
AIN
VOFFSET
VREF
GND
AVCC
GND
AVCC
TOP VIEW
(Not to Scale)
AD9042
cofired ceramic package forms a multilayer substrate to which
internal bypass capacitors and the 9042 die are attached and a
44-pin TQFP low profile surface mount package. The AD9042
industrial grade is specified from –40°C to +85°C. However,
the AD9042 was designed to perform over the full military
temperature range (–55°C to +125°C); consult factory for
military grade product options.
PRODUCT HIGHLIGHTSGuaranteed sample rate is 41 MSPS.Dynamic performance specified over entire Nyquist band;
spurious signals typ. 80 dBc for –1 dBFS input signals.Low power dissipation:595 mW off a single +5V supply.Reference and track-and-hold included on chip.Packaged in 28-pin ceramic DIP and 44-pin TQFP.
AD9042AST PIN DESIGNATIONS
DC SPECIFICATIONS
NOTESC1 (Pin 10 on AD9042AST only) tied to GND through 0.01μF capacitor.VREF is normally tied to VOFFSET through 50 Ω. If VREF is used to provide dc offset to other circuits, it should first be buffered.ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 μF capacitor.ENCODE may also be driven differentially in conjunction with ENCODE; see “Encoding the AD9042” for details.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
(AVCC = DVCC = +5V; VREF tied to VOFFSET through 50 Ω; TMIN = –408C, TMAX = +858C)1
(AVCC = DVCC = +5 V; ENCODE & ENCODE = 41 MSPS;
VREF tied to VOFFSET through 50 Ω; TMIN = –408C, TMAX = +858C)1
AD9042–SPECIFICATIONS
AC SPECIFICATIONS1
NOTESAll ac specifications tested by driving ENCODE and ENCODE differentially; see “ENCODING the AD9042” for details.C1 (Pin 10 on AD9042AST only) tied to GND through 0.01μF capacitor.Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed).Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD ) is the ratio of signal level to total noise + harmonics.Analog input signal power at –1 dBFS; worst spur is the ratio of the signal level to worst spur, usually limited by harmonics.Analog input signal power swept from –20 dBFS to –95 dBFS; dither power = –32.5 dBm; dither circuit used on input signal (see “Overcoming Static Nonlinearities
with Dither”); SFDR is ratio of converter full scale to worst spur.Tones at –7 dBFS (F1 = 15.3 MHz, F2 = 19.5 MHz); two tone intermodulation distortion (IMD) rejection is ratio of either tone to worst third order intermod product.Both input tones swept from –20 to –95 dBFS; Dither power = –32.5 dBm; dither circuit used on input signal (see “Overcoming Static Nonlinearities with Dither);
two tone spurious-free dynamic range (SFDR) is the ratio of converter full scale to worst spur.
Specifications subject to change without notice.
AD9042
(AVCC = DVCC = +5 V; ENCODE & ENCODE = 41 MSPS;
VREF tied to VOFFSET through 50 Ω; TMIN = –408C, TMAX = +858C)2
AD9042
ORDERING GUIDE
WAFER TEST LIMITS1
NOTESElectrical test is performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after
packaging is not guaranteed for standard product dice.Die substrate is connected to 0 V.
ABSOLUTE MAXIMUM RATINGS1
NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Typical thermal impedances for “D” package (custom ceramic 28-pin DIP):
θJC = 14°C/W; θJA = 34°C/W. For “ST” package (44-pin TQFP) ; θJA = 55°C/W.
(AVCC = DVCC = +5 V; ENCODE = 10.3 MSPS unless otherwise noted)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample
basis.
III–Sample tested only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C;
sample tested at temperature extremes.
AD9042AST PIN DESCRIPTIONS
(Most Significant Bit).
NOTEOutput coded as twos complement.
AD9042AD PIN DESCRIPTIONS
NOTEOutput coded as twos complement.
AD9042 CUSTOM 28-PIN DIP PACKAGE
AD9042
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of ENCODE
command and the time when all output data bits are within
valid logic levels.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal 150% of full scale is
reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1dB below full
scale) to the rms value of the sum of all other spectral
components, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. May be reported in
dBc (i.e., degrades as signal levels is lowered), or in dBFS
(always related back to converter full scale).
Transient Response
The time required for the converter to achieve 0.02%
accuracy when a one-half full-scale step function is applied to
the analog input.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product;
reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . . 155 × 168 × 21 (±1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2,605
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silver Filled
Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
DIE LAYOUT W/PAD LABELS
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve
rated performance; pulse width low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.
Figure 1.Timing Diagram
AIN
+3.5V
AVCC
Figure 2.Analog Input Stage
AVCC
ENCODEENCODE
Figure 3.Encode Inputs
AVCC
(PIN 10*)
VREF
*AD9042AST ONLY
INTERNAL NODE ON AD9042AD
DVCC
DVCC
D0–D11
Figure 5.Digital Output Stage
Figure 6.2.4 V Reference
+5V+5V200kHz
SINEWAVE
TTL CLOCK OSC.
49.9Ω
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
8.212.316.4
Figure 8. Single Tone at 1.2 MHz
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
8.212.316.4
Figure 9. Single Tone at 9.6 MHz
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
8.212.316.4
Figure 10. Single Tone at 19.5 MHz
AD9042–Typical Performance Characteristics
Figure 12. Noise vs. AIN
Figure 13. Harmonics vs. AIN
Figure 18. SNR, Worst Spurious vs. Duty Cycle
Figure 19. NPR Output Spectrum
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
8.212.316.4
Figure 14. Two Tones at 15.3 MHz & 19.5 MHz
ANALOG INPUT POWER LEVEL – dBFS
WORST CASE SPURIOUS – dBc AND dBFS
–60–50–40–30–20–10
Figure 15.AD9042AD Single Tone SFDR
INPUT POWER LEVEL (F1 = F2) – dBFS
WORST CASE SPURIOUS – dBc AND dBFS
–60–50–40–30–20–10
Figure 16. AD9042AD Two Tone SFDR
AD9042
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
8.212.316.4
Figure 20. 4K FFT without Dither
ANALOG INPUT POWER LEVEL – dBFS
WORST CASE SPURIOUS – dBc
–60–50–40–30–20–10
Figure 21.SFDR without Dither
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
8.212.316.4
Figure 22.128K FFT without Dither
Figure 23. 4K FFT with Dither
ANALOG INPUT POWER LEVEL – dBFS
WORST CASE SPURIOUS – dBc
–60–50–40–30–20–10
Figure 24. SFDR with Dither
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
8.212.316.4
Figure 25. 128K FFT with Dither
THEORY OF OPERATION
The AD9042 analog-to-digital converter (ADC) employs a two-
stage subrange architecture. This design approach ensures
12-bit accuracy, without the need for laser trim, at low power.
As shown in the functional block diagram, the 1 V p-p single-
ended analog input, centered at 2.4 V, drives a single-in to
differential-out amplifier, A1. The output of A1 drives the first
track-and-hold, TH1. The high state of the ENCODE pulse
places TH1 in hold mode. The held value of TH1 is applied to
the input of the 6-bit coarse ADC. The digital output of the
coarse ADC drives a 6-bit DAC; the DAC is 12 bits accurate.
The output of the 6-bit DAC is subtracted from the delayed
analog signal at the input to TH3 to generate a residue signal.
TH2 is used as an analog pipeline to null out the digital delay of
the coarse ADC.
The residue signal is passed to TH3 on a subsequent clock cycle
where the signal is amplified by the residue amplifier, A2, and
converted to a digital word by the 7-bit residue ADC. One bit
of overlap is used to accommodate any linearity errors in the
coarse ADC.
The 6-bit coarse ADC word and 7-bit residue word are added
together and corrected in the digital error correction logic to
generate the output word. The result is a 12-bit parallel digital
word which is CMOS-compatible, coded as twos complement.
APPLYING THE AD9042
Encoding the AD9042
The AD9042 is designed to interface with TTL and CMOS
logic families. The source used to drive the ENCODE pin(s)
must be clean and free from jitter. Sources with excessive jitter
will limit SNR (ref. Equation 1 under “Noise Floor and SNR”).
0.01µF
TTL OR CMOS
SOURCE
Figure 26.Single-Ended TTL/CMOS Encode
The AD9042 encode inputs are connected to a differential input
stage (see Figure 3 under EQUIVALENT CIRCUITS). With
no input connected to either the ENCODE or input, the voltage
dividers bias the inputs to 1.6 volts. For TTL or CMOS usage,
the encode source should be connected to ENCODE.
ENCODE should be decoupled using a low inductance or
microwave chip capacitor to ground. Devices such as AVX
05085C103MA15, a 0.01 μF capacitor, work well.
If a logic threshold other than the nominal 1.6 V is required, the
following equations show how to use an external resistor, RX, to
raise or lower the trip point (see Figure 3; R1 = 17k, R2 = 8k). =5R2RX1R2+R1RX+R2RX to lower logic threshold.
Figure 27.Lower Logic Threshold for Encode 1=5R2+R1RX+RX
to raise logic threshold.
0.01µF
ENCODE
SOURCE
AVCC
Figure 28.Raise Logic Threshold for Encode
While the single-ended encode will work well for many
applications, driving the encode differentially will provide
increased performance. Depending on circuit layout and system
noise, a 1dB to 3 dB improvement in SNR can be realized. It is
not recommended that differential TTL logic be used however,
because most TTL families that support complementary
outputs are not delay or slew rate matched. Instead, it is
recommended that the encode signal be ac-coupled into the
ENCODE and ENCODE pins.
The simplest option is shown below. The low jitter TTL signal
is coupled with a limiting resistor, typically 100 ohms, to the
primary side of an RF transformer (these transformers are
inexpensive and readily available; part# in Figure 29 is from
Mini-Circuits). The secondary side is connected to the
ENCODE and ENCODE pins of the converter. Since both
encode inputs are self biased, no additional components are
required.
Figure 29.TTL Source – Differential Encode
AD9042
If no TTL source is available, a clean sine wave may be
substituted. In the case of the sine source, the matching net-
work is shown below. Since the matching transformer specified
is a 1:1 impedance ratio, R, the load resistor should be selected
to match the source impedance. The input impedance of the
AD9042 is negligible in most cases.
T1-1TSINE
SOURCE
Figure 30.Sine Source – Differential Encode
If a low jitter ECL clock is available, another option is to ac-
couple a differential ECL signal to the encode input pins as
shown below. The capacitors shown here should be chip
capacitors but do not need to be of the low inductance variety.
–VS
Figure 31.Differential ECL for Encode
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
–VS
AD96687 (1/2)
Figure 32.ECL Comparator for Encode
Care should be taken not to overdrive the encode input pin
when ac coupled. Although the input circuitry is electrically
protected from over or under voltage conditions, improper
circuit operations may result from overdriving the encode input
pins.
Driving the Analog Input
Because the AD9042 operates off of a single +5V supply, the
analog input range is offset from ground by 2.4volts. The
analog input, AIN, is an operational amplifier configured in an
inverting mode (ref. Equivalent Circuits: Analog Input Stage).
VOFFSET is the noninverting input which is normally tied
through a 50ohm resistor to VREF (ref. Equivalent Circuits:
2.4 V Reference). Since the operational amplifier forces its
inputs to the same voltage, the inverting input is also at 2.4 volts.
amplifier offset; this reference is designed to track internal cir-
cuit shifts over temperature.
AD9042
250Ω
+2.4V
REFERENCE
AIN
THROUGH
50 OHMS
TIED TO
VREF
VOFFSET50Ω
0.1µF
Figure 33.Analog Input Offset by +2.4 V Reference
Although the AD9042 may be used in many applications, it was
specifically designed for communications systems which must
digitize wide signal bandwidths. As such, the analog input was
designed to be ac-coupled. Since most communications products
do not down-convert to dc, this should not pose a problem. One
example of a typical analog input circuit is shown below. In this
application, the analog input is coupled with a high quality chip
capacitor, the value of which can be chosen to provide a low
frequency cutoff that is consistent with the signal being
sampled; in most cases, a 0.1μF chip capacitor will work well.
Figure 34.AC-Coupled Analog Input Signal
Another option for ac-coupling is a transformer. The imped-
ance ratio and frequency characteristics of the transformer are
determined by examining the characteristics of the input signal
source (transformer primary connection), and the AD9042 in-
put characteristics (transformer secondary connection). “RT”
should be chosen to satisfy termination requirements of the
source, given the transformer turns ratio. A blocking capacitor
is required to prevent AD9042 dc bias currents from flowing
through the transformer.
Figure 35.Transformer-Coupled Analog Input Signal
When calculating the proper termination resistor, note that the
external load resistor is in parallel with the AD9042 analog
input resistance, 250 ohms. The external resistor value can be
calculated from the following equation:

Partno	Mfg	Dc	Qty	Available	Descript
AD9042AD	AD	N/a	10	avai	12-Bit, 41 MSPS Monolithic A/D Converter
AD9042AST	ADI	N/a	2	avai	12-Bit, 41 MSPS Monolithic A/D Converter