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AD8651ARM
50 MHz/ Precision/ Low Distortion/ Low Noise CMOS Amplifiers
50 MHz, Precision, Low Distortion,
Low Noise CMOS Amplifiers
Rev. B
FEATURES
Bandwidth: 50 MHz @ 5 V
Low Noise: 4.5 nV/√Hz
Offset voltage: 100 µV typ, specified over
entire common-mode range
41 V/µs slew rate
Rail-to-rail input and output swing
Input bias current: 1 pA
Single-supply operation: 2.7 V to 5.5 V
Space-saving MSOP and SOIC packaging
APPLICATIONS
Optical communications
Laser source drivers/controllers
Broadband communications
High speed ADC and DAC
Microwave link interface
Cell phone PA control
Video line driver
Audio
PIN CONFIGURATIONS
OUT
NC = NO CONNECT
AD8651
TOP VIEW
(Not to Scale)03301-0-001
Figure 1. 8-Lead MSOP (RM-8)
OUT A
–IN A
+IN A
OUT B
–IN B
+IN B
AD8652
TOP VIEW
(Not to Scale)03301-B
Figure 2. 8-Lead MSOP (RM-8)
–IN
+IN
OUT
NC = NO CONNECT03301-0-002
Figure 3. 8-Lead SOIC (R-8)
OUT A
–IN A
+IN A
OUT B
–IN B
+IN B03301-B
Figure 4. 8-Lead SOIC (R-8)
GENERAL DESCRIPTION The AD8651 is a high precision, low noise, low distortion, rail-
to-rail CMOS operational amplifier that runs from a single-
supply voltage of 2.7 V to 5 V.
The AD8651 is a rail-to-rail input and output amplifier with a
gain bandwidth of 50 MHz and a typical voltage offset of
100 µV across common mode from a 5 V supply. It also features
low noise—4.5 nV/√Hz.
The AD8651 can be used in communications applications, such
as cell phone transmission power control, fiber optic
networking, wireless networking, and video line drivers.
The AD8651 features the newest generation of DigiTrim®
in-package trimming. This new generation measures and
corrects the offset over the entire input common-mode range,
providing less distortion from VOS variation than is typical of
other rail-to-rail amplifiers. Offset voltage and CMRR are both
specified and guaranteed over the entire common-mode range
as well as over the extended industrial temperature range.
The AD8651 is offered in the 8-lead SOIC package and the
8-lead MSOP package. It is specified over the extended indus-
trial temperature range (−40°C to +125°C).
TABLE OF CONTENTS Electrical Characteristics.................................................................3
Electrical Characteristics.................................................................4
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Typical Performance Characteristics.............................................6
Applications.....................................................................................14
Theory of Operation..................................................................14
Rail-to-Rail Output Stage......................................................14
Rail-to-Rail Input Stage.........................................................14
Input Protection.....................................................................15
Overdrive Recovery...............................................................15
Layout, Grounding, and Bypassing considerations...............15
Power Supply Bypassing........................................................15
Grounding...............................................................................15
Leakage Currents....................................................................15
Input Capacitance..................................................................15
Output Capacitance...............................................................16
Settling Time...........................................................................16
THD Readings vs. Common-Mode Voltage......................16
Driving a 16-Bit ADC............................................................17
Outline Dimensions.......................................................................18
Ordering Guide..........................................................................18
REVISION HISTORY
9/04—Data Sheet Changed from Rev. A to Rev. B Added AD8652....................................................................Universal
Change to General Description.......................................................1
Changes to Electrical Characteristics.............................................3
Changes to Absolute Maximum Ratings........................................5
Change to Figure 23..........................................................................9
Change to Figure 26..........................................................................9
Change to Figure 36........................................................................11
Change to Figure 42........................................................................12
Change to Figure 49........................................................................13
Change to Figure 51........................................................................13
Inserted Figure 52............................................................................13
Change to Theory of Operation section.......................................14
Change to Input Protection section..............................................15
Changes to Ordering Guide...........................................................20
6/04—Changed from REV. 0 to REV. A Change to Figure 18.............................................................................8
Change to Figure 21.............................................................................9
Change to Figure 29.............................................................................10
Change to Figure 30.............................................................................10
Change to Figure 43.............................................................................12
Change to Figure 44.............................................................................12
Change to Figure 47.............................................................................13
Change to Figure 57.............................................................................17
ELECTRICAL CHARACTERISTICS
Table 1. V+ = 2.7 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified
ELECTRICAL CHARACTERISTICS
Table 2. V+ = 5 V, V– = 0 V, VCM = V+/2, TA = 25°C, unless otherwise specified
ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 3. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. 1 θJA is specified for the worst-case conditions, i.e., θJA is specified for device
soldered in circuit board for surface-mount packages.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TYPICAL PERFORMANCE CHARACTERISTICS
VOS (µV)
NUMBE
R OF AMP
IFIE
12016020003301-B
Figure 5. Input Offset Voltage Distribution
TEMPERATURE (°C)
–5005010015003301-B
Figure 6. Input Offset Voltage vs. Temperature
NUMBE
R OF AMP
IFIE
TCVOS (µV/°C)23456789101103301-B
Figure 7. TCVOS Distribution
COMMON-MODE VOLTAGE (V)2345603301-B
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
INP
T BAIS
CURRE
NT (pA)
TEMPERATURE (°C)4014012010080602003301-B
Figure 9. Input Bias Current vs. Temperature
CURRE
NT (mA)
SUPPLY VOLTAGE (V)5431603301-B
Figure 10. Supply Current vs. Supply Voltage
CURRE
NT (mA)
TEMPERATURE (°C)
–5005010015003301-B
Figure 11. Supply Current vs. Temperature
– V
OUT
(mV
CURRENT LOAD (mA)2040601008003301-B
Figure 12. Output Voltage to Supply Rail vs. Load Current
OUTPUT SW
ING HIGH (
TEMPERATURE (°C)
–5005010015003301-B
Figure 13. Output Voltage Swing High vs. Temperature
OUTPUT SW
ING LOW
TEMPERATURE (°C)
–5005010015003301-B
Figure 14. Output Voltage Swing Low vs. Temperature
CMRR (dB)
FREQUENCY (Hz)1k10M1M100k10k10003301-B
Figure 15. CMRR vs. Frequency
CMRR (dB)
TEMPERATURE (°C)
–5005010015003301-B
Figure 16. CMRR vs. Temperature
CMRR (dB)
TEMPERATURE (°C)
–5005010015003301-B
Figure 17. CMRR vs. Temperature
RR (dB)
FREQUENCY (Hz)101001k10k100k1M10M100M03301-B
Figure 18. PSRR vs. Frequency
RR (dB)
TEMPERATURE (°C)
–5005010015003301-B
Figure 19. PSRR vs. Temperature
VOLTA
GE N
ISE D
ITY (
Hz)
FREQUENCY (Hz)1k100k10k10003301-B
Figure 20. Voltage Noise Density vs. Frequency
CURRE
NT NOIS
DE
ITY
(fA/
Hz)
FREQUENCY (Hz)
1001k100k10k03301-B
Figure 21. Current Noise Density vs. Frequency
VOLTA
GE (
V/D
IV)
TIME (200µs/DIV)03301-B
Figure 22. No Phase Reversal
OPEN-
OOP GAIN (
SE (
egrees)
FREQUENCY (Hz)1001k10k100k1M10M100M03301-B
Figure 23. Open-Loop Gain and Phase vs. Frequency
(dB)
TEMPERATURE (°C)
–5005010015003301-B
Figure 24. Open-Loop Gain vs. Temperature
OPEN-
OOP GAIN (
OUTPUT VOLTAGE SWING FROM THE RAILS (mV)5010015025020003301-B
Figure 25. Open-Loop Gain vs. Output Voltage Swing
FREQUENCY (Hz)
CLOSED-
OOP GAIN (–40
50k5M500k50M300M03301-B
Figure 26. Closed-Loop Gain vs. Frequency
MAX
IMUM O
UT S
ING
(V
FREQUENCY (Hz)
100k100M10M1M03301-B
Figure 27. Maximum Output Swing vs. Frequency
VOLTA
GE (
V/D
IV)
TIME (100µs/DIV)03301-B
Figure 28. Large Signal Response
VOLTA
GE (
100mV/D
IV)
TIME (10µs/DIV)03301-B
Figure 29. Small Signal Response
L SIGN
OVER
OOT (
CAPACITANCE (pF)
020605040301003301-B
Figure 30. Small Signal Overshoot vs. Load Capacitance
TIME (200ns/DIV)
–200mV
2.5V03301-B
Figure 31. Negative Overload Recovery Time
TIME (200ns/DIV)
–2.5V03301-B
Figure 32. Positive Overload Recovery Time
OUTP
UT IMP
DANCE
FREQUENCY (Hz)10001000001000010003301-B
Figure 33. Output Impedance vs. Frequency
VOS (µV)
NUMBE
R OF AMP
IFIE
12016020003301-B
Figure 34. Input Offset Voltage Distribution
