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AD8391ARADN/a1avai+3.3 V to +12 V xDSL Line Drive Amplifier with Power Down


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AD8391AR
+3.3 V to +12 V xDSL Line Drive Amplifier with Power Down
REV.A
xDSL Line Driver
3V to 12V with Power-Down
PRODUCT DESCRIPTION

The AD8391 consists of two parallel, low cost xDSL line drive
amplifiers capable of driving low distortion signals while running on
both 3V to 12V single-supply or equivalent dual-supply rails. It is
primarily intended for use in single-supply xDSL systems where low
power is essential, such as line powered and battery backup systems.
Each amplifier output drives more than 250mA of current while
maintaining –82dBc of SFDR at 100kHz on 12V, outstanding
performance for any xDSL CPE application.
The AD8391 provides a flexible power-down feature consisting of
a 1-pin digital control line. This allows biasing of the AD8391 to
full power (Logic 1), standby (Logic three-state maintains low
amplifier output impedance), and shutdown (Logic 0 places
amplifier outputs in a high impedance state). PWDN is refer-
enced to –VS.
Fabricated on ADI’s high speed XFCB process, the high bandwidth
and fast slew rate of the AD8391 keep distortion to a minimum,
while dissipating a minimum of power. The quiescent current of the
AD8391 is low: 19 mA total static current draw.The AD8391
comes in a compact 8-lead SOIC “thermal coastline” package and
operates over the temperature range –40°C to +85°C.
Figure 1.Upstream Transit Spectrum with Empty Bin
at 45kHz; Line Power = 12.5 dBm into 100 Ω
PIN CONFIGURATION
8-Lead SOIC
(Thermal Coastline)
FEATURES
Ideal xDSL Line Driver for VoDSL or Low Power
Applications such as USB, PCMCIA, or PCI Based
Customer Premise Equipment (CPE)
High Output Voltage and Current Drive
340 mA Output Drive Current
Low Power Operation
3 V to 12 V Power Supply Range
1-Pin Logic Controlled Standby, Shutdown
Low Supply Current of 19 mA (Typical)
Low Distortion
–82 dBc SFDR, 12 V p-p into Differential 21 � @ 100 kHz
4.5 nV/√Hz Input Voltage Noise Density, 100 kHz
Out-of-Band SFDR = –72 dBc, 144 kHz to 500 kHz,
ZLINE = 100 �, PLINE = 13.5 dBm
High Speed
40 MHz Bandwidth (–3 dB)
375 V/�s Slew Rate
APPLICATIONS
VoDSL Modems
xDSL USB, PCI, PCMCIA Cards
Line Powered or Battery Backup xDSL Modems
AD8391–SPECIFICATIONS
INPUT CHARACTERISTICS
POWER SUPPLY
Specifications subject to change without notice.
(@ 25�C, VS=12 V, RL = 10 �, VMID = VS/2, G=–2, RF=909 �, RG=453 �,
unless otherwise noted. See TPC 1 for Basic Circuit Configuration.)
SPECIFICATIONS25�C, VS=3 V, RL = 10 �, VMID = VS/2, G=–2, RF=909 �, RG=453 �, unless otherwise noted.
See TPC 1 for Basic Circuit Configuration.)
AD8391

Specifications subject to change without notice.
AD8391
ABSOLUTE MAXIMUM RATINGS1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation2
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . 650mW
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Logic Voltage, PWDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short-Circuit Duration
. . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curve
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device on a 4-layer board in free air at 85°C:8-Lead SOIC
package: �JA = 100°C/W.
MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the
AD8391 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for a plastic encapsu-
lated device is determined by the glass transition temperature of
the plastic, approximately 150°C. Temporarily exceeding this
limit may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package.
To ensure proper operation, it is necessary to observe the maxi-
mum power derating curve.
Figure 2.Plot of Maximum Power Dissipation
vs. Temperature
ORDERING GUIDE
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8391 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
TPC 1.Single-Ended Test Circuit
TPC 2.Small Signal Step Response
TIME – ns
OUTPUT V
GE
– V
1007550250125150175200225250

TPC 3.Large Signal Step Response
TPC 4.Small Signal Step Response
TPC 5.Large Signal Step Response
TPC 6.0.1% Settling Time
AD8391
TPC 7.Output Voltage vs. Frequency
TPC 8.Output Saturation Voltage vs. Load
TPC 9.Small Signal Frequency Response
TPC 10.Output Voltage vs. Frequency
TPC 11.Output Saturation Voltage vs. Load
TPC 12.Small Signal Frequency Response
TPC 13.Voltage Noise vs. Frequency (RTI)
TPC 14.Output Impedance vs. Frequency
TPC 15.Crosstalk (Output to Output)
vs. Frequency
TPC 16.Current Noise vs. Frequency (RTI)
TPC 17.Output Impedance vs. Frequency
TPC 18.Signal Feedthrough vs. Frequency
AD8391
TPC 19.Differential Output Test Setup
TPC 20.Differential Distortion vs. Output Voltage
TPC 21.MTPR vs. Transformer Turns Ratio
TPC 22.Differential Distortion vs. Frequency
TPC 23.Differential Distortion vs. Output Voltage
TPC 24.SFDR vs. Transformer Turns Ratio
TPC 25.Single-Ended Distortion vs. Peak
Output Current
TPC 26.Overload Recovery
TPC 27.Single-Ended Distortion vs. Peak
Output Current
TPC 28.Overload Recovery
AD8391
Figure 3.Simplified Schematic
Figure 4.Model of Current Feedback Amplifier
Feedback Resistor Selection

In current feedback amplifiers, selection of the feedback and
gain resistors will impact distortion, bandwidth, noise, and gain
flatness. Care should be exercised in the selection of these resistors
so that the optimum performance is achieved. Table I shows the
recommended resistor values for use in a variety of gain settings for
the test circuits in TPC 1 and TPC 19. These values are only
intended to be a starting point when designing for any application.
Table I.Resistor Selection Guide
GENERAL INFORMATION
Theory of Operation

The AD8391 is a dual current feedback amplifier with high
output current capability. It is fabricated on Analog Devices’
proprietary eXtra Fast Complementary Bipolar Process (XFCB) that
enables the construction of PNP and NPN transistors with fT’s
greater than 3 GHz. The process uses dielectrically isolated
transistors to eliminate the parasitic and latch-up problems caused
by junction isolation. These features enable the construction of
high frequency, low distortion amplifiers.
The AD8391 has a unique pin out. The two noninverting inputs
of the amplifier are connected to the VMID pin, which is internally
biased by two 5kΩ resistors forming a voltage divider between
+VS and –VS. VMID is accessible through Pin 7. There is also a
10 pF internal capacitor from VMID to –VS. The two inverting pins
are available at Pin 1 and Pin 8, allowing the gain of the amplifiers to
be set with external resistors. See Page 1 for a connection diagram
of the AD8391.
A simplified schematic of an amplifier is shown in Figure 3.
Emitter followers buffer the positive input, VP, to provide low
input current and current noise. The low impedance current
feedback summing junction is at the negative input, VN. The
output stage is another high gain amplifier used as an integrator
to provide frequency compensation. The complementary common-
emitter output provides the extended output swing.
A current feedback amplifier’s bandwidth and distortion perfor-
mance are relatively insensitive to its closed-loop signal gain,
which is a distinct advantage over a voltage-feedback architecture.
Figure 4 shows a simplified model of a current feedback amplifier.
The feedback signal is an error current that flows into the inverting
node. RIN is inversely proportional to the transconductance of
the amplifier’s input stage, gmi. Circuit analysis of the pictured
follower with gain circuit yields:
where:
Recognizing that G × RIN << RF , and that the –3 dB point is set
when Tz(s) = RF, one can see that the amplifier’s bandwidth
depends primarily on the feedback resistor. There is a value of
RF below which the amplifier will be unstable, as the amplifier
will have additional poles that will contribute excess phase shift.
The optimum value for RF depends on the gain and the amount
of peaking tolerable in the application. For more information
about current feedback amplifiers, see ADI’s high speed design
techniques at /technology/amplifiersLinear/
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