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AD8367ARUADIN/a996avai500 MHz, Linear-in-dB VGA with AGC Detector
AD8367ARU-REEL7 |AD8367ARUREEL7ADN/a9avai500 MHz, Linear-in-dB VGA with AGC Detector


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AD8367ARU-AD8367ARU-REEL7
500 MHz, Linear-in-dB VGA with AGC Detector
REV.0
500 MHz, Linear-in-dB VGA
with AGC Detector
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Broad Range Analog Variable Gain
–2.5 dB to +42.5 dB
3 dB Cutoff Frequency of 500 MHz
Gain Up and Gain Down Modes
Linear-in-dB, Scaled 20 mV/dB
Resistive Ground Referenced Input
Nominal ZIN � 200 �
On-Chip Square-Law Detector
Single-Supply Operation: 2.7 V to 5.5 V
APPLICATIONS
Cellular Base Station
Broadband Access
Power Amplifier Control Loops
Complete, Linear IF AGC Amplifiers
High-Speed Data I/O
GENERAL DESCRIPTION

The AD8367 is a high-performance 45dB variable gain ampli-
fier with linear-in-dB gain control for use from low frequencies
up to several hundred megahertz. The range, flatness, and accu-
racy of the gain response are achieved using Analog Devices’
X-AMP® architecture, the most recent in a series of powerful
proprietary concepts for variable gain applications, which far
surpasses what can be achieved using competing techniques.
The input is applied to a 200Ω resistive ladder network, having
nine sections each of 5dB loss, for a total attenuation of 45dB.
At maximum gain, the first tap is selected; at progressively lower
gains, the tap moves smoothly and continuously toward higher
attenuation values. The attenuator is followed by a 42.5dB
fixed gain feedback amplifier—essentially an operational ampli-
fier with a gain bandwidth product of 100GHz—and is very
linear, even at high frequencies. The output third order intercept is
+20dBV at 100MHz (+27dBm re 200Ω), measured at an
output level of 1Vp-p with VS= 5V.
The analog gain-control interface is very simple to use. It is
scaled at 20mV/dB, and the control voltage, VGAIN, runs frommV at –2.5dB to 950mV at +42.5dB. In the inverse-gain
mode of operation, selected by a simple pin-strap, the gain
decreases from +42.5dB at VGAIN = 50 mV to –2.5 dB at
VGAIN = 950 mV. This inverse mode is needed in AGC applications,
which are supported by the integrated square-law detector,
whose set point is chosen to level the output to 354mV rms,
regardless of the waveshape. A single external capacitor sets up
the loop averaging time.
The AD8367 may be powered on or off by a voltage applied to
the ENBL pin. When this voltage is at a logic LO, the total power
dissipation drops to the milliwatt range. For a logic HI, the chip
powers-up rapidly to its normal quiescent current of 26mA at
25°C. The AD8367 is available in a 14-lead TSSOP package for
the industrial temperature range of –40°Cto +85°C.
X-AMP is a registered trademark of Analog Devices, Inc.
AD8367–SPECIFICATIONS
(VS = 5V, TA = 25�C, System Impedance ZO = 200 �, VMODE = 5 V, f = 10 MHz,
unless otherwise noted.)

INPUT STAGE
GAIN CONTROL INTERFACE
f = 140 MHz
f = 190 MHz
f = 240 MHz
NOTESThe output dc centering voltage is normally set at VS�2 and can be adjusted by applying a voltage to DECL.
Specifications subject to change without notice.
AD8367
AD8367
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8367 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*

Supply Voltage VPSO, VPSI . . . . . . . . . . . . . . . . . . . . . 5.5 V
ENBL Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS + 200 mV
MODE Select Voltage . . . . . . . . . . . . . . . . . . . . VS + 200 mV
VGAIN Control Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±600mV
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250mW
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . 125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
TPC 1.Gain vs. Frequency for Values of VGAIN
TPC 2.Gain vs. VGAIN (Mode LO and Mode HI)
TPC 3.Gain Conformance at 70 MHz for T � –40�C,
+25�C, and +85�C.
TPC 4.NF (re 200 Ω) vs. Frequency at Maximum Gain
TPC 5.NF (re 200 �) vs. VGAIN at 70 MHz

TPC 6.OIP3 vs. VGAIN
AD8367
TPC 7.OIP3 vs. Frequency for VGAIN � 500 mV
TPC 8.Output P1dB vs. VGAIN
TPC 9.Output P1dB vs. Frequency at VGAIN � 500 mV
TPC 10.IMD3 vs. Gain (VOUT � 1 V p-p Composite)
TPC 11.Output Compression Point vs. Supply
Voltage at 70 MHz, VGAIN = 500 mV
TPC 12.Output Third Order Intercept vs. Supply
Voltage at 70 MHz, VGAIN = 500 mV
TPC 13.Input Resistance and Series Reactance vs.
Frequency at VGAIN = 500 mV
300mV
330

TPC 14.Input Reflection Coefficient vs. Frequency
from 10 MHz to 500 MHz for Multiple Values of VGAIN
330

TPC 16.Output Reflection Coefficient vs. Frequency
from 10MHzto 500MHz for Multiple Values of VGAIN
TPC 17.VGA Time Domain Response (3 dB Step)
AD8367
TPC 19.AGC RSSI (Voltage on DETO Pin) vs. Input
Power at 10 MHz, 70 MHz, 140 MHz, and 240 MHz
TPC 20.AGC RSSI (Voltage on DETO Pin) vs. Input
Power over Temperature at 70 MHz
TPC 21.AGC RSSI (Voltage on DETO Pin) vs. Input
Power for Various Modulation Schemes
TPC 22.AGC Time Domain Response (3 dB Step)

TPC 23.Gain Scaling Distribution at 70 MHz

TPC 24.Gain Intercept Distribution at 70 MHz
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