AD8321AR-REEL ,Gain Programmable CATV Line DriverFEATURES FUNCTIONAL BLOCK DIAGRAMLinear in dB Gain Response Over >53 dB RangeVCC GNDDrives Low Dist ..
AD8322ARU ,5 V CATV Line Driver Coarse Step Output Power ControlFEATURES FUNCTIONAL BLOCK DIAGRAMSupports DOCSIS Standard for Reverse PathV (7 PINS)CCTransmissionG ..
AD8322ARU-REEL ,5 V CATV Line Driver Coarse Step Output Power Controlapplications such as cable@ MAX GAINmodems that are designed to the MCNS-DOCSIS upstream –60standar ..
AD8323 ,5 V CATV Line Driver Fine Stepapplications such as cableP = 60dBmV @ MAX GAINOmodems that are designed to the MCNS-DOCSIS upstrea ..
AD8323ARU ,5 V CATV Line Driver Fine Step Output Power ControlCHARACTERISTICSSpecified AC Voltage Output = 60 dBmV, Max Gain 116 mV p-pNoise Figure Max Gain, f = ..
AD8323ARU ,5 V CATV Line Driver Fine Step Output Power Controlapplications such as cableP = 60dBmV @ MAX GAINOmodems that are designed to the MCNS-DOCSIS upstrea ..
ADP3293JCPZ-RL , 8-Bit, Programmable 2- to 3-Phase Synchronous Buck Controller
ADP3300ART-2.7 ,0.3-16V; high accuracy anyCAP 50mA low dropout linear regulator. For cellular telephones, notebook, palmtop computers, battery powered systems, PCMCIA regulators, bar code scanners, camcoders, camerasSPECIFICATIONS otherwise noted)Parameter Symbol Conditions Min Typ Max UnitOUTPUT VOLTAGE V V = V 0 ..
ADP3300ART-2.7-RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorFEATURES FUNCTIONAL BLOCK DIAGRAMHigh Accuracy Over Line and Load: 0.8% @ 25C,1.4% Over Temperat ..
ADP3300ART-2.7-RL7 ,High Accuracy anyCAP® 50 mA Low Dropout Linear RegulatorSPECIFICATIONS otherwise noted)Parameter Symbol Conditions Min Typ Max UnitOUTPUT VOLTAGE V V = V 0 ..
ADP3300ART-2.85 ,0.3-16V; high accuracy anyCAP 50mA low dropout linear regulator. For cellular telephones, notebook, palmtop computers, battery powered systems, PCMCIA regulators, bar code scanners, camcoders, camerasSpecifications subject to change without notice.–2– REV. BADP3300ABSOLUTE MAXIMUM RATINGS* PIN FUNC ..
ADP3300ART-3 ,High Accuracy anyCAP 50 mA Low Dropout Linear RegulatorSpecifications subject to change without notice.REV. A–2–ADP3300ABSOLUTE MAXIMUM RATINGS*PIN FUNCTI ..
AD8321AR-AD8321AR-REEL
Gain Programmable CATV Line Driver
REV.0
Gain Programmable
CATV Line Driver
FEATURES
Linear in dB Gain Response Over >53 dB Range
Drives Low Distortion >11 dBm Signal into 75 V Load:
–53 dBc SFDR at 42 MHz
Very Low Output Noise Level
Maintains Constant 75 V Output Impedance
Power-Up and Power-Down Condition
No Line Transformer Required
Upper Bandwidth: 235 MHz (Min Gain)V Single Supply Operation
Power-Down Functionality
Supports SPI Interface
Low Cost
APPLICATIONS
Gain Programmable Line Driver
HFC High Speed Data Modems
Interactive CATV Set-Top Boxes
CATV Plant Test Equipment
General Purpose IF Variable Gain Block
DESCRIPTIONThe AD8321 is a low cost digitally controlled variable gain
amplifier optimized for coaxial line driving applications such as
cable modems that are designed to the DOCSIS* (upstream)
standard. An 8-bit serial word determines the desired output
gain over a 53.4 dB range, resulting in gain changes of 0.75 dB/
LSB.
The AD8321 comprises a digitally controlled variable attenuator
of 0 dB to –53.4 dB, which is preceded by a low noise, fixed
gain buffer and followed by a low distortion high power ampli-
fier. The AD8321 accepts a differential or single-ended input
signal. The output is specified for driving a 75 W load, such as
coaxial cable, although the AD8321 is capable of driving other
loads. Performance of –53 dBc is achieved with an output level
up to 11 dBm at 42 MHz bandwidth using a 9 V supply.
A key performance and cost advantage of the AD8321 results
from the ability to maintain a constant 75 W output impedance
during power-up and power-down conditions. This eliminates
the need for external 75 W termination, resulting in twice the
effective output voltage when compared to a standard opera-
tional amplifier, thus eliminating the need for a transformer.
*Data-Over-Cable Service Interface Specifications
FUNCTIONAL BLOCK DIAGRAM
DATENCLK
VIN+
VIN–
VOUT
GNDVCC
SDATAThe AD8321 is packaged in a low cost 20-lead SOIC, operates
from a single +9V supply, and has an operational temperature
range of –40°C to +85°C.
Figure 1.Harmonic Distortion vs. Gain Control
AD8321–SPECIFICATIONSSpecifications subject to change without notice.
(@ VCC = +9 V, TA = +258C, VIN = 0.137 V p-p, single-ended input, RL = 75V, RIN =
V unless otherwise noted)
LOGIC INPUTS (TTL/CMOS Logic)Logic “1” Current (VINH = 5 V) PD
TIMING REQUIREMENTSClock Period (TC)
Setup Time SDATA vs. Clock (TDS)
TEH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PEDESTAL
CLK
SDATA
DATEN
TONFigure 2.Serial Interface Timing
VALID DATA BIT
TDS
SDATA
CLK
(DATEN, CLK, SDATA, VCC = +9 V; Full Temperature Range)
(Full Temperature Range, VCC = +9 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
AD8321
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8321 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*Thermal Resistance measured on SEMI standard 4-layer board.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage +VS
Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V
Input Voltages
Pins 18, 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V
Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
VOUT
VCC
VCC
CLK
DATEN
GND
VCC
BYP1
GND
GND
VIN–
VCC
BYP2
GND
GND
SDATAVCC
GND
VIN+
PIN FUNCTION DESCRIPTIONS
GAIN CONTROL – Decimal
GAIN ERROR – dB
–0.6Figure 4.Gain Error vs. Gain Control
FREQUENCY – MHz10100
OUTPUT NOISE – nV/Figure 7.Output Referred Noise vs.
Frequency
FUNDAMENTAL FREQUENCY – MHz
DISTORTION – dBc1525455565–59
–47Figure 10.Third Order Harmonic
Distortion vs. Frequency for Various
Input Levels
GAIN CONTROL – Decimal
OUTPUT NOISE – nV/081624324048566472Figure 6.Output Referred Noise vs.
Gain Control
FUNDAMENTAL FREQUENCY – MHz
DISTORTION – dBc1525455565–59
–47Figure 9.Second Order Harmonic
Distortion vs. Frequency for Various
Input Levels
Figure 12.Third Order Intercept vs.
Frequency
FREQUENCY – MHz
GAIN – dB
–10101001000Figure 5.AC Response
GAIN CONTROL – Decimal
DISTORTION – dBc164048566472–80
–30Figure 8.Harmonic Distortion vs.
Gain Control
FREQUENCY – MHz
OUT
– dBm
41.441.842.242.643.0Figure 11.Two-Tone Intermodula-
tion Distortion
AD8321
FREQUENCY – MHz10100
GAIN – dBFigure 13.AC Response for Various
Capacitor Loads
Figure 16.Clock Feedthrough
Figure 19.Overload Recovery
Figure 15.Power Up/Power Down
Glitch
Figure 18.Output Settling Time Due
to Input Change
TEMPERATURE – 8C
– mA–505075100
–25025Figure 21.Supply Current vs.
Temperature
Figure 14.Power Up/Power Down
Glitch
FREQUENCY – MHz
FEEDTHROUGH – dB
–20Figure 17.Input Signal Feedthrough
vs. Frequency
FREQUENCY – MHz10100
IMPEDANCE – Figure 20.Output Impedance vs.
Frequency
OPERATIONAL DESCRIPTIONThe AD8321 is a digitally controlled variable gain power ampli-
fier that is optimized for driving a 75 W cable. As a multifunc-
tional bipolar device on a single silicon die, it incorporates all
the analog features necessary to accommodate reverse path
(upstream) high speed (5 MHz to 65 MHz) cable data modem
requirements. The AD8321 has an overall gain range of ap-
proximately 53 dB and is capable of greater than 100 MHz
operation at output signal levels exceeding 12 dBm. Overall,
when considering the device’s wide gain range, low distortion,
wide bandwidth and variable load drive, the device can be used
in many variable gain block applications.
DATENCLK
VIN+
VIN–
VOUT
GNDVCC
SDATAFigure 22.Functional Block Diagram
The digitally programmable gain is controlled by the three-wire
“SPI” compatible inputs. These inputs are called SDATA
(serial data input port), DATEN (data enable low input port)
and CLK (clock input port). See Pin Function Descriptions
and Functional Block diagram. The AD8321 is programmed by
an 8-bit “attenuator” word. When a standard 8-bit word is
used, the first data bit MSB will be shifted out of the 7-bit shift
register during the eighth rising CLK edge. The lower seven
bits will then be loaded into the AD8321’s digital decode sec-
tion when the DATEN input is taken high.
The gain of the AD8321 is linear in steps of 0.7526 dB. The
gain transfer function starts at –27.43 dB (at decimal code 0)
and increases 0.7526 dB/LSB. The gain increases up to decimal
code 71. At this point the gain is at its maximum level of 26 dB.
If a decimal word between 71 and 127 is entered, the gain is no
longer incremented and stays at 26 dB. Since the MSB of an 8-bit
word is a “don’t care” bit, at decimal code 128, the AD8321’s
gain returns to its minimum value. The gain vs. gain control
relationship repeats itself as shown in Figure 23 for the upper
127 codes.
The gain transfer function is as follows:
AV =26 dB – ((71 – CODE) · 0.7526 dB) for CODE £ 71
AV = 26 dB for 71 £ CODE £ 127
AV =26 dB + ((199 – CODE) · 0.7526 dB) for 128 £
CODE £ 199
AV =26 dB for 199 £ CODE £ 255
where CODE is the decimal equivalent of the 8-bit word loaded in
the AD8321’s data latch (see Figure 23).
GAIN CODE – Decimal
GAIN – dB
–202241921601286496Figure 23.Linear-In dB Gain vs. Gain Control
The AD8321 is composed of four analog functions in the
power-up or forward mode. The input amplifier (preamp) which
can be used single-endedly or differentially and provides a maxi-
mum of 12 dB of attenuation. If the input is used in the differ-
ential configuration, it is imperative that the input signals are
180 degrees out of phase and of equal amplitudes. This will
ensure the proper gain accuracy and harmonic performance.
The preamp stage drives a vernier stage that provides the fine
tune gain adjustment. The 0.7526 dB step resolution is imple-
mented in this stage. After the vernier stage, a DAC provides the
bulk of the AD8321’s attenuation (six bits or 36 dB). The signals
in the preamp and vernier gain blocks are differential to im-
prove the PSRR and linearity. A single-ended current is fed
from the DAC into the output stage, which amplifies this cur-
rent to the appropriate level necessary to drive a 75 W load. The
output stage utilizes negative feedback to implement a
75 W output impedance. This eliminates the need for an exter-
nal 75 W matching resistor needed in typical video (or video
filter) termination requirements.
AD8321The attenuation setting in the AD8321 is determined by the
8-bit word in the data latch. The SDATA load sequence is
initiated by a falling edge on DATEN. The gain control data
(SDATA) is serially loaded (MSB first) into the 7-bit shift register
at each rising edge of the clock. See Figure 24. While DATEN
is low, the data latch holds the previous data word allowing the
attenuation level to remain unchanged. After eight clock cycles
the new data word is fully loaded and DATEN is switched high.
This enables the data latch and the loaded register data is passed to
the attenuator with the updated gain value. Also at this DATEN
transition, the internal clock is disabled, thus inhibiting new
serial input data.
The power amplifier has two basic modes of operation. A for-
ward mode (or power-up mode) and a reverse mode (or power-
down) mode. In the power-up mode (PD = 1), the power
amplifier stage is enabled and the AD8321 has a maximum gain
of 20 V/V or 26 dB (into 75 W). With a total attenuation of
53.43 dB in the DAC, vernier and preamp, the AD8321’s total
gain range is 26 dB to –27.43 dB. In both the forward or reverse
mode the single-ended output signal maintains a dc level of
VCC/2. This dc output level provides for optimum large signal
linearity.
In the power-down mode (PD = 0), the power amplifier is
turned off and a “reverse” amplifier (the inner triangle in Figure
22) is enabled. During this 1-to-0 transition, the output power
is disabled. This assures that S11 and S22 remain approximately
equal to zero thus minimizing line reflections. In the time do-
main, as PD switches states, a transitional glitch and pedestal
offset results (See Figures 14 and 15). These anomalies have
been minimized by temperature compensated internal circuitry
and laser trimming. The powered down supply current drops to
52 mA versus 90 mA in the power-up mode.
APPLICATIONS
General ApplicationThe AD8321 is primarily intended for use as the return path
(also called upstream path) Power Amplifier (PA) or line driver
in cable modem applications. Upstream data is modulated in
either QPSK or QAM format. This is done either in DSP or by
a dedicated QPSK/QAM modulator such as the AD9853 or
other modem/modulator chip. The amplifier receives its input
signal either from the dedicated QPSK/QAM modulator or from
a DAC. In both cases, the signal must be low-pass filtered be-
fore being applied to the line driving amplifier. Because the
distance to the central office varies from cable modem sub-
scriber to subscriber, resulting in various line losses, signals from
various subscribers will require attenuation while others may
require gain. As a result, the AD8321 line driver is required to
vary its output applying attenuation or gain as needed so that all
signals arriving at the central office are of the same amplitude.
DOCSIS (Data Over Cable Service Interface Specifications)
requires a cable modem output signal ranging in power from a
minimum of 8 dBmV to a maximum of 58 dBmV. In cable
modem applications where DOCSIS compliance is desired, the
AD8321 amplifier must be used in conjunction with a 75 W
matching attenuator connected between the AD8321 output
and the low-pass input port of the diplexer. See the schematic in
Figure 28. The matching attenuator is used to achieve DOCSIS-
compliant noise levels at the lower end of the AD8321 output
power range. The insertion loss of a diplexer is typically less
than 1 dB. As a result of these combined losses, the PA line
driver must be capable of delivering sufficient power into a 75 W
load while maintaining reasonable distortion performance at the
output of the modem. (See sections containing “DOCSIS” for
further information. All references to DOCSIS pertain to
SP-RFI-I04-980724 entitled Radio Frequency Interface
Specification.)
GAIN TRANSFER (G2)
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PEDESTAL
CLK
SDATA
DATEN
TONFigure 24.Serial Interface Timing
Basic ConnectionFigure 25 shows the basic schematic for operating the AD8321
in single-ended inverting mode. To operate in inverting mode,
connect the input signal through an ac coupling capacitor to
VIN–; VIN+ should be decoupled to ground with a 0.1 mF
capacitor. Because the amplifier operates from a single supply,
and the differential input pins are biased to approximately
VCC/2, the differential inputs must be ac-coupled using 0.1 mF
capacitors. For operation in the noninverting mode, the VIN–
pin should be decoupled to ground via a 0.1 mF capacitor, with
the input signal being fed to the AD8321 through the (ac-coupled)
VIN+ pin. Inverting mode should be chosen if the AD8321 is
being used as a drop-in replacement for the AD8320 (the
AD8321 predecessor). Balanced differential inputs to the
AD8321 may also be applied at an amplitude that is one-half
the specified single-ended input amplitude. See the Differential
Inputs section for more on this mode of operation.
Power Supply and DecouplingThe AD8321 should be powered with a good quality (i.e., low
noise) single supply of 9 V. Although the AD8321 circuit will
function at voltages lower than 9 V, optimum performance will
not be achieved at lower supply settings. Careful attention must
be paid to decoupling the power supply pins. A 10 mF capacitor
located in near proximity to the AD8321 is required to provide
good decoupling for lower frequency signals. In addition, and
more importantly, five 0.1 mF decoupling capacitors should be
located close to each of the five power supply pins (7, 8, 9, 17
and 20). A 0.1 mF capacitor must also be connected to the pins
labeled BYP1 and BYP2 (Pins 5 and 14) to provide decoupling
to internal nodes of the device. All six ground pins should be
connected to a common low impedance ground plane.
Input Bias, Impedance and TerminationOn the input side, the VIN+ and VIN– have a dc bias level
equal to (VCC/2)–0.2 V. The input signal must therefore be ac-
coupled before being applied to either input pin. The input
impedance, when operated in single-ended mode is roughly
820 W (900 W in differential mode). An external shunt resis-
tance (R1) to ground of 82.5 W is required to create a single-
ended input impedance of close to 75 W. If single-ended 50 W
termination is required, a 53.6 W shunt resistor may be used.
Differential input operation may be achieved by using a shunt
resistor of 41 W to ground on each of the inputs, or 82.6 W
across the inputs resulting in a differential input impedance of
approximately 75 W. Note: to avoid dc loading of either the
VIN+ or VIN– pin, the ac-coupling capacitor must be placed
between the input pin(s) and the shunt resistor(s). Refer to the
Differential Inputs section for more details on this mode of
operation.
Output Bias, Impedance and TerminationOn the output side, the VOUT pin is also dc-biased to VCC/2 or
midway between the supply voltage and ground. The output
signal must therefore be ac-coupled before being applied to the
load. The dc-bias voltage is available on the BYP1 and BYP2
pins (Pins 5 and 14 respectively) and can be used in dc-biasing
schemes. These nodes must be decoupled to ground using a
0.1 mF capacitor as shown in Figure 25. If the BYP1 and/or
BYP2 voltages are used externally, they should be buffered.
External back termination resistors are not required when using
the AD8321. The output impedance of the AD8321 is 75 W and
is maintained dynamically. This on chip back termination is
maintained regardless of whether the amplifier is in forward
transmit mode or reverse powered down mode. If the output
signal is being evaluated on 50 W test equipment such as a spec-
trum analyzer, a 75 W to 50 W adapter (commonly called a mini-
mum loss pad) should be used to maintain a properly matched
circuit.
DATEN
0.1mF
0.1mF
0.1mF
82.5V
INPUT
DATEN
CLK
SDATA
0.1mF
DIPLEXER
RIN = 75V
VCC
+9V
10mF
AD8321
Varying the Gain and SPI ProgrammingThe gain of the AD8321 can be varied over a range of 53 dB
from approximately –27 dB to +26 dB, in increments of ap-
proximately 0.7526 dB per LSB. Programming the gain of the
AD8321 is accomplished using conventional Serial Peripheral
Interface or SPI protocol. Three digital lines, DATEN, CLK
and SDATA, are used to stream eight bits of data into the serial
shift register of the AD8321. Changing the state of the DATEN
port from Logic 1-to-0 starts the load sequence by activating the
CLK line. No changes in output signal are realized during this
transition. Subsequently, any data applied to SDATA is clocked
into the serial shift register Most Significant Bit (MSB) first and
on the rising edge of each CLK pulse. The AD8321 may be
programmed to deliver maximum gain (+26 dB) at decimal
code 71. As a result, only the last seven bits of a typical 8-bit
SPI word effect the gain resulting in the gain response depicted
in Figure 22. Since the SPI codes from 0 through 71 appear
digitally identical to codes 128 through 199 for all bits except
the MSB, the AD8321 repeats the gain vs. decimal code re-
sponse twice in the 256 available codes (see Operational De-
scription for gain equations and Figure 23 for Gain Response).
The MSB of a typical SPI word (i.e., the first data bit presented
to the SDATA line after the DATEN transition from logic 1 to
0 and prior to the rising edge of the first clock pulse) is disre-
garded or ignored. Data enters the serial shift register through
the SDATA port on the rising edge of the next seven CLK
pulses. Returning the DATEN line to Logic 1 latches the con-
tent of the shift register into the attenuator core resulting in a
well controlled change in output signal level. The timing dia-
gram for AD8321’s serial interface is shown in Figure 24.
Gain Dependence on Load ImpedanceThe AD8321 has a dynamic output impedance of 75 W. This
dynamic output impedance is trimmed to provide a maximum
gain of +26 dB when loaded with 75 W. Operating the AD8321
at load impedances other than 75 W will only change the gain of
the AD8321 while the specified gain range of 53 dB is unchanged.
Varying the load impedance will result in 6 dB of additional gain
when RLOAD approaches infinity. The relationship between
RLOAD and gain is depicted in Figure 26 and is described by the
following equation:
Gain (dB) = [20 log ((2 · RLOAD)/(RLOAD +75))]+(26–(0.7526 ·
(71-Code)))
0500
GAIN – dB
Between Burst On/Off Transients, Asynchronous Power-
Down and DOCSISA 42% reduction in consumed power may be achieved asyn-
chronously by applying Logic 0 to PD Pin 6 activating the on-
chip “reverse amplifier.” The supply current is then reduced to
approximately 52 mA and the modem can no longer transmit in
the upstream direction. The on-chip reverse amplifier is de-
signed to reduce “between burst noise” and maintain a 75 W
source impedance to the low pass port of the modem’s diplexer
while minimizing power consumption. Changing the logic level
applied to the PD pin will result in a Burst On/Off Transient at
the output of the AD8321. The transient results from switching
between the forward transmit amplifier and the powered down
(reverse) amplifier. Although the resulting transient meets the
DOCSIS transient amplitude requirements at maximum gain, it
is the lower gain range (i.e., 8 dBmV to 31 dBmV) where the
AD8321 may exceed the 7 mV maximum. The diplexer may
further reduce the glitch amplitude. An external RF switch, such
as Alpha Industries AS128-73 GaAs 2 Watt High Linearity
SPDT RF switch, may be used to further reduce the spurious
emissions, improve the isolation between the cable plant and the
upstream line driver and switch in a 75 W back termination
required to maintain proper line termination to the LP port of
the diplexer (see Figure 28).
Noise and DOCSISOne of the most difficult issues facing designers of DOCSIS
compliant modems is maintaining a quiet output from the PA
during times when no information is being transmitted up-
stream. In addition, maintaining proper signal-to-noise ratios
serves to ensure the quality of transmitted data. This is extremely
critical when the output signal of the modem is set to the mini-
mum DOCSIS specified output level or 8 dBmV. The AD8321
output noise spectral density at minimum gain (or 8 dBmV) is
20 nV/√Hz measured at 10 MHz. Considering the “Spurious
Emissions in 5 MHz to 42 MHz” of Table 4–8 in DOCSIS, the
calculated noise power in dBmV for 160 K sym/sec is:
Comparing the computed noise power to the signal at 8 dBmV
yields –49.5 dBc or 3.5 dB higher than the required –53 dBc in
DOCSIS Table 4–8. An attenuator designed to match the
AD8321 75 W source to the 75 W load may be required. Refer-
ring to the schematic of Figure 28 and the evaluation board
silkscreen of Figure 31, the matching attenuator is comprised of
the three resistors referred to as Rc, Rd and Re. Select the at-
tenuation level from Table I such that noise floor is reduced to
levels specified in DOCSIS.
Table I.
