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AD8109
325 MHz, 8x8 Buffered Video Crosspoint Switch (Gain=1)
REV.A
325 MHz, 8 � 8 Buffered Video
Crosspoint Switches
FUNCTIONAL BLOCK DIAGRAM
FEATURES
8 � 8 High-Speed Nonblocking Switch Arrays
AD8108: G = +1
AD8109: G = +2
Serial or Parallel Programming of Switch Array
Serial Data Out Allows “Daisy Chaining” of Multiple
8 � 8s to Create Larger Switch Arrays
Output Disable Allows Connection of Multiple Devices
Pin-Compatible with AD8110/AD8111 16 � 8 Switch
Arrays
For 16 � 16 Arrays See AD8116
Complete Solution
Buffered Inputs
Eight Output Amplifiers,
AD8108 (G = +1),
AD8109 (G = +2)
Drives 150 � Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.02%/0.02� Differential Gain/Differential Phase Error
(RL = 150 �)
Excellent AC Performance
AD8108AD8109
–3 dB Bandwidth325 MHz250 MHz
Slew Rate400 V/�s480 V/�s
Low Power of 45 mA
Low All Hostile Crosstalk of –83 dB @ 5 MHz
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “Power-
On” Reset Capability)
Excellent ESD Rating: Exceeds 4000 V Human Body
Model
80-Lead LQFP Package (12 mm � 12 mm)
APPLICATIONS
Routing of High-Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM.)
Component Video (YUV, RGB)
Compressed Video (MPEG, Wavelet)
3-Level Digital Video (HDB3)
PRODUCT DESCRIPTIONThe AD8108 and AD8109 are high-speed 8 × 8 video cross-
point switch matrices. They offer a –3 dB signal bandwidth
greater than 250 MHz and channel switch times of less than
25 ns with 1% settling. With –83 dB of crosstalk and –98 dB
isolation (@ 5 MHz), the AD8108/AD8109 are useful in many
high-speed applications. The differential gain and differential
phase of better than 0.02% and 0.02° respectively along with
0.1 dB flatness out to 60 MHz make the AD8108/AD8109 ideal
for video signal switching.
The AD8108 and AD8109 include eight independent output buff-
ers that can be placed into a high impedance state for paralleling
crosspoint outputs so that off channels do not load the output bus.
The AD8108 has a gain of +1, while the AD8109 offers a gain
of +2. They operate on voltage supplies of ±5 V while consuming
only 45 mA of idle current. The channel switching is performed via
a serial digital control (which can accommodate “daisy chaining”
of several devices) or via a parallel control allowing updating of
an individual output without re-programing the entire array.
The AD8108/AD8109 is packaged in an 80-lead LQFP package
and is available over the extended industrial temperature range
of –40°C to +85°C.
*Patent Pending.
AD8108/AD8109–SPECIFICATIONSNOISE/DISTORTION PERFORMANCE
OPERATING TEMPERATURE RANGE
(VS = �5 V, TA = +25�C, RL = 1 k� unless otherwise noted)
TIMING CHARACTERISTICS (Serial)CLK Pulsewidth
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK to UPDATE Delay
UPDATE Pulsewidth
CLK to DATA OUT Valid, Serial Mode
Figure 1.Timing Diagram, Serial Mode
Table I.Logic Levels
AD8108/AD8109
Table II.Logic Levels
TIMING CHARACTERISTICS (Parallel)CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
Figure 2.Timing Diagram, Parallel Mode
ABSOLUTE MAXIMUM RATINGS1Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 V
Internal Power Dissipation2
AD8108/AD8109 80-Lead Plastic LQFP (ST) . . . . . 2.6 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . .–65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . .300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air (TA = 25°C):
80-lead plastic LQFP (ST): θJA = 48°C/W.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8108/AD8109 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the
AD8108/AD8109 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem-
perature of the plastic, approximately 150°C.Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
While the AD8108/AD8109 is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions.To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 3.
Figure 3.Maximum Power Dissipation vs. Temperature
AD8108/AD8109
PIN CONFIGURATION
DGNDDVCCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCDVCCDGNDRESET
AGND07
AVEE06/07
OUT06
AGND06
AVCC05/06
OUT05
AGND05
AVEE04/05
OUT04
AGND04
AVCC03/04
OUT03
AGND03
AVEE02/03
OUT02
AGND02
AVCC01/02
OUT01
AGND01
AVEE00/01
DATA OUT
CLK
DATA IN
UPDATE
SER/PAR
AGND
AVEE
AVCC
AVCC00
AGND00
OUT00
NC = NO CONNECT
IN00
IN01
AGND
AGND
IN03
IN04
AGND
AGND
IN06
IN07
AGND
AVCC
AVCC07
OUT07
AGND
IN02
AGND
IN05
AGND
AVEE
PIN FUNCTION DESCRIPTIONSFigure 5.I/O SchematicsLogic Inpute.Logic Output
AD8108/AD8109Figure 4.Logic Diagram
Table III.Operation Truth TableFREQUENCY – Hz
GAIN
dB
100k1M1G10M100M
FLATNESS
dBTPC 1.AD8108 Frequency Response
TPC 2.AD8108 Crosstalk vs. Frequency
FREQUENCY – Hz
100k1M10M100M
DISTORTION
dB
–100TPC 3.AD8108 Distortion vs. Frequency
TPC 4.AD8108 Step Response, 100 mV Step
TPC 5.AD8108 Step Response, 2 V Step
TPC 6.AD8108 Settling Time
AD8108/AD8109
FREQUENCY – Hz
GAIN
dB
100k1M1G10M100M
FLATNESS
dB
–0.4TPC 7.AD8109 Frequency Response
TPC 8.AD8109 Crosstalk vs. Frequency
TPC 9.AD8109 Distortion vs. Frequency
TPC 10.AD8109 Step Response, 100 mV Step
TPC 11.AD8109 Step Response, 2 V Step
TPC 12.AD8109 Settling Time
TPC 13.AD8108 PSRR vs. Frequency
TPC 14.AD8108 Voltage Noise vs. Frequency
OUTPUT IMPEDANCE
FREQUENCY – MHz
100k
10k
100TPC 15.AD8108 Output Impedance, Disabled
TPC 16.AD8108 Switching Transient (Glitch)
TPC 17.AD8108 Off Isolation, Input-Output
TPC 18.AD8108 Output Impedance, Enabled
AD8108/AD8109TPC 19.AD8109 PSRR vs. Frequency
TPC 20.AD8109 Voltage Noise vs. Frequency
TPC 21.AD8109 Output Impedance, Disabled
TPC 22.AD8109 Switching Transient (Glitch)
TPC 23.AD8109 Off Isolation, Input-Output
TPC 24.AD8109 Output Impedance, Enabled
INPUT IMPEDANCE 500M10M100M100k
FREQUENCY – Hz
30k
100k
10k
100TPC 25.AD8108 Input Impedance vs. Frequency
TPC 26.AD8108 Frequency Response vs. Capacitive Load
TPC 27.AD8108 Flatness vs. Capacitive Load
TPC 28.AD8108 Switching Time
TPC 29.AD8108 Offset Voltage Distribution
TPC 30.AD8108 Offset Voltage Drift vs. Temperature
(Normalized at 25°C)
AD8108/AD8109
INPUT IMPEDANCE 500M10M100M100k
FREQUENCY – Hz
30k
100k
10k
100TPC 31.AD8109 Input Impedance vs. Frequency
TPC 32.AD8109 Frequency Response vs. Capacitive
Load
TPC 33.AD8109 Flatness vs. Capacitive Load
TPC 34.AD8109 Switching Time
TPC 35.AD8109 Offset Voltage Distribution (RTI)
TEMPERATURE – �C
mV
–40–20020406080100TPC 36.AD8109 Offset Voltage Drift vs. Temperature
(Normalized at 25°C)
