AD809BR Fast Delivery |IC PHOENIX CO.,LIMITED

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AD809BR
155.52 MHz Frequency Synthesizer
REV.A155.52 MHz Frequency Synthesizer
FEATURES
Frequency Synthesis to 155.52 MHz
19.44 MHz or 9.72 MHz Input
Reference Signal Select Mux
Single Supply Operation: +5 V or –5.2 V
Output Jitter: 2.0 Degrees RMS
Low Power: 90 mW
10 KH ECL/PECL Compatible Output
10 KH ECL/PECL/TTL/CMOS Compatible Input
Package: 16-Pin Narrow 150 Mil SOIC
155.52 Mbps ports. The AD809 can be applied to create the trans-
mit bit clock for one or more ports.
An input signal multiplexer supports loop-timed applications
where a 155.52 MHz transmit bit clock is recovered from the
155.52 Mbps received data.
The low jitter VCO, low power and wide operating temperature
range make the device suitable for generating a 155.52 MHz bit
clock for SONET/SDH/Fiber in the Loop systems.
The device has a low cost, on-chip VCO that locks to either
8× or 16× the frequency at the 19.44 MHz or 9.72 MHz input.
No external components are needed for frequency synthesis; how-
ever, the user can adjust loop dynamics through selection of a
damping factor capacitor whose value determines loop damping.
The AD809 design guarantees that the clock output frequency
will drift low (by roughly 20%) in the absence of a signal at the
input.
The AD809 consumes 90 mW and operates from a single power
supply at either +5 V or –5.2 V.
PRODUCT DESCRIPTION
The AD809 provides a 155.52 MHz ECL/PECL output clock from
either a 19.44 MHz or a 9.72 MHz TTL/CMOS/ECL/PECL refer-
ence frequency. The AD809 functionality supports a distributed
timing architecture, allowing a backplane or PCB 19.44 MHz or
9.72 MHz timing reference signal to be distributed to multiple
FUNCTIONAL BLOCK DIAGRAMCLKOUTN
(155MHz
PECL
OUTPUT)
CLKIN
TTL/CMOSIN
(155MHz)
MUX
CF1CF2
CLKOUT
(19.44MHz
9.72MHz)CLKINN
PECLIN
PECLINN
AD809–SPECIFICATIONS
OUTPUT JITTER
JITTER TRANSFER
DUTY CYCLE TOLERANCE
INPUT VOLTAGE LEVELS
OUTPUT VOLTAGE LEVELS
OUTPUT RISE/FALL TIMES 1.5
NOTESDevice design is guaranteed for operation over Capture Ranges and Tracking Ranges, however the device has wider capture and tracking ranges
(for both ×8 and ×16 synthesis).
Specifications subject to change without notice.
(TA = TMIN to TMAX, VS = VMIN to VMAX, CD = 22 nF, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS*
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+12V
Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . .VCC + 0.6 V
Maximum Junction Temperature. . . . . . . . . . . . . . . . .+165°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature Range (Soldering10sec) . . . . . . . .+300°C
ESD Rating (Human Body Model) . . . . . . . . . . . . . . . .1500 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics:
16-Pin Narrow Body SOIC Package: θJA = 110°C/W.
ORDERING GUIDE
OUTPUT 50%
(PINS 4 & 5)
SYMMETRY = (100 × tON/τ)
Figure 1.Symmetry
Table I.
Table II.Applying a PECL/ECL or CMOS/TTL Reference
Input to the AD809
AD809 Phase Skew
The AD809 output is in phase with the input. The falling edge
at Pin 4, CLKOUTN, occurs 700 ps before the rising edge at
Pin 10, TTL/CMOSIN at 27°C. The phase skew remains rela-
tively constant over temperature. Refer to Table III for phase
skew data.
Table III.Phase Skew vs. Temperature
Temperature
PIN DESCRIPTIONS
PIN CONFIGURATION
PECLINN
CLKIN
AVCC2
MUX
VEE
PECLIN
VCC2
CLKOUTN
TTL/CMOSIN
AVCC1
CLKINNCLKOUT
VCC1
CF1
CF2AVEE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD809 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD809
DEFINITION OF TERMS
Maximum, Minimum and Typical Specifications
Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the distribu-
tion. This procedure is intended to tolerate production varia-
tions: if the mean shifts by 1.5 standard deviations, the remaining
4.5 standard deviations still provide a failure rate of only 3.4
parts per million. For all tested parameters, the test limits are
guardbanded to account for tester variation to thus guarantee
that no device is shipped outside of data sheet
specifications.
Capture and Tracking Range
This is the range of input data rates over which the AD809 will
remain in lock.
Jitter
This is the dynamic displacement of digital signal edges from
their long term average positions, measured in degrees rms.
Jitter on the input clock causes jitter on the synthesized clock.
Output Jitter
This is the jitter on the synthesized clock (OUTPUT, OUTPUT),
in degrees rms.
Jitter Transfer
The AD809 exhibits a low-pass filter response to jitter applied
to its input data.
Bandwidth
This describes the frequency at which the AD809 attenuates
sinusoidal input jitter by 3 dB.
Peaking
This describes the maximum jitter gain of the AD809 in dB.
Damping Factor, z
Damping factor, ζ describes the compensation of the second or-
der PLL. A larger value of ζ corresponds to more damping and
less peaking in the jitter transfer function.
Duty Cycle Tolerance
The AD809 exhibits a duty cycle tolerance that is measured
by applying an input signal (nominal input frequency) with a
known duty cycle imbalance and measuring the ×8 or ×16
output frequency.
Symmetry-Recovered Clock Duty Cycle
Symmetry is calculated as (100× on time)/period, where on time
equals the time that the clock signal is greater than the midpoint
between its “0” level and its “1” level.
Typical Characteristic Curves
Figure 2.Jitter Histogram
Figure 3.Jitter vs. Input Duty Cycle
USING THE AD809
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10 μF capacitor between VCC and ground is recom-
mended. Care should be taken to isolate the +5 V power trace
to VCC2 (Pin 3). The VCC2 pin is used inside the device to pro-
vide the CLKOUT/CLKOUTN signals.
Use of a trace connecting Pin 14 and Pin 6 (AVCC2 and VCC1
respectively) is recommended. Use of 0.1 μF capacitors between
IC power supply and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to the schematic, Figure 5, for advised connections.
Transmission Lines
Use of 50 Ω transmission lines are recommended for PECL
inputs.
Terminations
Termination resistors should be used for PECL input signals.
Metal, thick film, 1% tolerance resistors are recommended.
Termination resistors for the PECL input signals should be
placed as close as possible to the PECL input pins.
Connections from the power supply to load resistors for input
and output signals should be individual, not daisy chained. This
will avoid crosstalk on these signals.
Loop Damping Capacitor, CD
A ceramic capacitor may be used for the loop damping capaci-
tor. A 22 nF capacitor provides a damping factor of 10.
Synthesizer Input
TTL/CMOSIN
Synthesizer Input
CLKIN/CLKINN
PECL INPUT
PLL Differential
Output Stage–
CLKOUT/CLKOUTN
Figure 4.Simplified Schematics
MUX
+5V
0.1µFR16
+5VGND
TP4TP3
0.1µF
VECTOR PINS SPACED FOR THROUGH-HOLE
CAPACITOR ON VECTOR CUPS.
COMPONENT SHOWN FOR REFERENCE ONLY.
ECL INN
ECL IN
CLKOUTN
CLKOUTC2 0.1µF
50Ω STRIP LINE
EQUAL LENGTH
JUMPER
CLKIN
CLKINN
CMOS/TTL IN
C12
0.1µF
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPx TEST POINTS ARE VECTOR PINS
AD809
Figure 6.Evaluation Board: Component Side

Partno	Mfg	Dc	Qty	Available	Descript
AD809BR	ADI	N/a	652	avai	155.52 MHz Frequency Synthesizer