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AD8045ACPZ-R2 |AD8045ACPZR2ADN/a2514avai3 nV/√Hz Ultralow Distortion Voltage Feedback High Speed Amplifier


AD8045ACPZ-R2 ,3 nV/√Hz Ultralow Distortion Voltage Feedback High Speed AmplifierSPECIFICATIONS WITH ±5 V SUPPLY TA = 25°C, G = +1, RS = 100 Ω, R L = 1 kΩ to ground, unless noted o ..
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AD8045ACPZ-R2
3 nV/√Hz Ultralow Distortion Voltage Feedback High Speed Amplifier
3 nV/√Hz Ultralow Distortion,
High Speed Op Amp

Rev. A
FEATURES
Ultralow distortion
SFDR
−101 dBc @ 5 MHz
−90 dBc @ 20 MHz
−63 dBc @ 70 MHz
Third-order intercept
43 dBm @ 10 MHz
Low noise
3 nV/√Hz
3 pA/√Hz
High speed
1 GHz, −3 dB bandwidth (G = +1)
1350 V/µs slew rate
7.5 ns settling time to 0.1%
Standard and low distortion pinout
Supply current: 15 mA
Offset voltage: 1.0 mV max
Wide supply voltage range: 3.3 V to 12 V
APPLICATIONS
Instrumentation
IF and baseband amplifiers
Active filters
ADC drivers
DAC buffers
CONNECTION DIAGRAMS NC
–IN
+IN

04814-0-001
Figure 1. 8-Lead AD8045 LFCSP (CP-8)
04814-0-001FEEDBACK–IN+IN
–VS
+VS
OUTPUT

Figure 2. 8-Lead AD8045 SOIC/EP (RD-8)
GENERAL DESCRIPTION

The AD8045 is a unity gain stable voltage feedback amplifier
with ultralow distortion, low noise, and high slew rate. With a
spurious-free dynamic range of −90 dBc @ 20 MHz, the
AD8045 is an ideal solution in a variety of applications,
including ultrasound, ATE, active filters, and ADC drivers.
ADI’s proprietary next generation XFCB process and innovative
architecture enables such high performance amplifiers.
The AD8045 features a low distortion pinout for the LFCSP,
which improves second harmonic distortion and simplifies the
layout of the circuit board.
The AD8045 has 1 GHz bandwidth, 1350 V/µs slew rate, and
settles to 0.1% in 7.5 ns. With a wide supply voltage range (3.3 V
to 12 V) and low offset voltage (200 µV), the AD8045 is an ideal
candidate for systems that require high dynamic range, preci-
sion, and high speed.
The AD8045 amplifier is available in a 3 mm × 3 mm LFCSP
and the standard 8-lead SOIC. Both packages feature an
exposed paddle that provides a low thermal resistance path to
the PCB. This enables more efficient heat transfer, and increases
reliability. The AD8045 works over the extended industrial
temperature range (−40°C to +125°C).
04814-0-079FREQUENCY (MHz)
HARM
ONI
DI
STORTI
ON (dBc)
–110

Figure 3. Harmonic Distortion vs. Frequency for Various Packages
TABLE OF CONTENTS
Specifications with ±5 V Supply.....................................................3
Specifications with +5 V Supply.....................................................4
Absolute Maximum Ratings............................................................5
Thermal Resistance......................................................................5
ESD Caution..................................................................................5
Pin Configurations and Function Descriptions...........................6
Typical Performance Characteristics.............................................7
Circuit Configurations...................................................................16
Wideband Operation.................................................................16
Theory of Operation......................................................................17
Frequency Response...................................................................17
DC Errors....................................................................................17
Output Noise...............................................................................18
Applications.....................................................................................19
Low Distortion Pinout...............................................................19
High Speed ADC Driver...........................................................19
90 MHz Active Low-Pass Filter (LPF).....................................20
Printed Circuit Board Layout.......................................................22
Signal Routing.............................................................................22
Power Supply Bypassing............................................................22
Grounding...................................................................................22
Exposed Paddle...........................................................................23
Driving Capacitive Loads..........................................................23
Outline Dimensions.......................................................................24
Ordering Guide..........................................................................24
REVISION HISTORY
9/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Features.........................................................................1
Changes to Specifications...............................................................4
Changes to Figure 58.....................................................................15
Changes to Figure 63.....................................................................17
Changes to Frequency Response Section...................................17
Changes to Figure 64.....................................................................17
Changes to DC Errors Section.....................................................17
Changes to Figure 65.....................................................................17
Changes to Figure 66.....................................................................18
Changes to Output Noise Section...............................................18
Changes to Ordering Guide.........................................................24
7/04—Revision 0: Initial Version

SPECIFICATIONS WITH ±5 V SUPPLY
TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to ground, unless noted otherwise. Exposed paddle must be floating or connected to −VS.
Table 1.
SPECIFICATIONS WITH +5 V SUPPLY
TA = 25°C, G = +1, RS = 100 Ω, RL = 1 kΩ to midsupply, unless otherwise noted. Exposed paddle must be floating or connected to −VS.
Table 2.
ABSOLUTE MAXIMUM RATINGS
Table 3.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE

θJA is specified for the worst-case conditions, i.e., θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance

Maximum Power Dissipation

The maximum safe power dissipation for the AD8045 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric perform-
ance of the AD8045. Exceeding a junction temperature of
175°C for an extended period of time can result in changes in
silicon devices, potentially causing degradation or loss of
functionality.
The power dissipated in the package (PD) is the sum of the qui-
escent power dissipation and the power dissipated in the die
due to the AD8045 drive at the output. The quiescent power is
the voltage between the supply pins (VS) times the quiescent
current (IS).
PD = Quiescent Power + (Total Drive Power – Load Power)
OUT
OUTSSDR–RIVP⎟⎟⎠⎜⎜⎝×+×=
RMS output voltages should be considered. If RL is referenced to
−VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply. )SDRIVP4+×=
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduce θJA.
Figure 4 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
04814-0-080AMBIENT TEMPERATURE (°C)
XIM
POW
ISSIPA
TION
0.5

Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
FEEDBACK
–IN
+IN
–VS
+VS
OUTPUT
NC = NO CONNECT
Figure 5. SOIC Pin Configuration
+VS
OUTPUT
–VS
Figure 6 . 8-Lead LFCSP Pin Configuration
Note: The exposed paddle must be connected to −VS or it must be electrically isolated (floating).
Table 5. 8-Lead SOIC Pin Function Descriptions

Table 6. 8-Lead LFCSP Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS
04814-0-049FREQUENCY (MHz)
NORMALIZE
CLOS
-LOOP
GAIN (dB)

Figure 7. Small Signal Frequency Response for Various Gains
04814-0-050FREQUENCY (MHz)
CLOSED-
OOP GAIN (

Figure 8. Small Signal Frequency Response for Various Loads
04814-0-051FREQUENCY (MHz)
CLOSED-
OOP GAIN (

Figure 9. Small Signal Frequency Response for Various Supplies
04814-0-048FREQUENCY (MHz)
CLOSED-
OOP GAIN (

Figure 10. Small Signal Frequency Response for Various Capacitive Loads
04814-0-052FREQUENCY (MHz)
CLOSED-
OOP GAIN (

Figure 11. Small Signal Frequency Response for Various Temperatures
04814-0-039FREQUENCY (MHz)10100
CLOSED-
OOP GAIN (
5.7

Figure 12. 0.1 dB Flatness vs. Frequency for Various Output Voltages
04814-0-043FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–10

Figure 13. Large Signal Frequency Response for Various Supplies
04814-0-042FREQUENCY (MHz)
CLOSED-
OOP GAIN (
–10

Figure 14. Large Signal Frequency Response for Various Loads
04814-0-041FREQUENCY (MHz)
NORMALIZE
CLOS
-LOOP
GAIN (dB)

Figure 15. Large Signal Frequency Response for Various Gains
04814-0-064FREQUENCY (MHz)
OPEN
OOP PH
SE (
egrees)
OPEN-
OOP GAIN (
–10

Figure 16. Open-Loop Gain and Phase vs. Frequency
04814-0-030FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–120

Figure 17. Harmonic Distortion vs. Frequency for Various Packages
04814-0-028FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–120

Figure 18. Harmonic Distortion vs. Frequency for Various Packages
04814-0-032FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–110

Figure 19. Harmonic Distortion vs. Frequency for Various Packages
04814-0-036FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–110

Figure 20. Harmonic Distortion vs. Frequency for Various Packages
04814-0-037FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–110

Figure 21. Harmonic Distortion vs. Frequency for Various Packages
04814-0-033FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–110

Figure 22. Harmonic Distortion vs. Frequency for Various Packages
04814-0-034FREQUENCY (MHz)
HARMONIC
DIS
ORTION (dBc
–110

Figure 23. Harmonic Distortion vs. Frequency for Various Packages
04814-0-025OUTPUT AMPLITUDE (V p-p)01234576
HARMONIC DIS
ORTION (dBc
–120

Figure 24. Harmonic Distortion vs. Output Voltage for Various Packages
04814-0-024OUTPUT AMPLITUDE (V p-p)01234576
HARMONIC DIS
ORTION (dBc
–110

Figure 25. Harmonic Distortion vs. Output Voltage for Various Packages
04814-0-026OUTPUT VOLTAGE (V p-p)01234567
HARMONIC DIS
ORTION (dBc
–120

Figure 26. Harmonic Distortion vs. Output Voltage
04814-0-027OUTPUT VOLTAGE (V p-p)01234567
HARMONIC DIS
ORTION (dBc
–120

Figure 27. Harmonic Distortion vs. Output Voltage
04814-0-029FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–100

Figure 28. Harmonic Distortion vs. Frequency for Various Packages
04814-0-031FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–90

Figure 29. Harmonic Distortion vs. Frequency for Various Packages
04814-0-035FREQUENCY (MHz)
HARMONIC DIS
ORTION (dBc
–100

Figure 30. Harmonic Distortion vs. Frequency for Various Packages
04814-0-022OUTPUT VOLTAGE (V p-p)
HARMONIC DIS
ORTION (dBc
–110

Figure 31. Harmonic Distortion vs. Output Voltage for Various Packages
04814-0-023OUTPUT VOLTAGE (V p-p)
HARMONIC DIS
ORTION (dBc
–110

Figure 32. Harmonic Distortion vs. Output Voltage for Various Packages
04814-0-076OUTPUT VOLTAGE STEP (V)01234
SLEW
E (
200

Figure 33. Slew Rate vs. Output Voltage
04814-0-012TIME (ns)05101520
OUTPUT VOLTAGE (
–0.15

Figure 34. Small Signal Transient Response for Various Supplies and Loads
TIME (ns)05101520
OUTPUT VOLTAGE (V)
–0.15
Figure 35. Small Signal Transient Response for Various Supplies and Loads
04814-0-014TIME (ns)05101520
OUTPUT VOLTAGE (V)
–0.15

Figure 36. Small Signal Transient Response for Various Loads
04814-0-015TIME (ns)05101520
OUTPUT VOLTAGE (
–0.20

Figure 37. Small Signal Transient Response with Capacitive Load
04814-0-016TIME (ns)05101520
OUTPUT VOLTAGE (V)

Figure 38. Large Signal Transient Response for Various Loads
04814-0-017TIME (ns)05101520
OUTPUT VOLTAGE (V)

Figure 39. Large Signal Transient Response for Various Supplies
04814-0-018TIME (ns)05101520
OUTPUT VOLTAGE (

Figure 40. Large Signal Transient Response with Capacitive Load
04814-0-019TIME (ns)05101520
OUTPUT VOLTAGE (V)

Figure 41. Large Signal Transient Response, Inverting
04814-0-061TIME (ns)
INP
T AND OUTP
UT V
LTAGE
(V

Figure 42. Input Overdrive Recovery
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