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AD8026AR-AD8026AR-REEL7
Quad High Speed Amplifier
REV.0
Quad High Speed
Amplifier
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DESCRIPTIONThe AD8026 is a complete low cost, closed loop, voltage feed-
back, quad amplifier. Precision trimmed resistors set a fixed RF/
RG ratio of 5/3 to a typical gain accuracy of 0.02%. Manufac-
tured on ADI’s proprietary XFCB high speed bipolar process,
which enables the output drivers to settle to within 0.1% within
55 ns into a 100pF load (4 V swing) and drive output voltages
to rated settling time to within 0.5V from the rail. The typical
3 dB bandwidth is 60 MHz, at G = +2.67. The AD8026 is
laser trimmed to produce both exceptional offset and gain
performance.
The low settling time, high slew rate, low offset and rail-to-rail
output voltage drive capability makes the AD8026 ideal for
driving LCD displays.
The AD8026 is available in a 14-lead SOIC package.
FEATURES
Voltage Feedback, Rail-to-Rail Output
Rated Settling Time to Within 0.5 V of Supply Rail
Quad High Speed Amplifier
Settling Time to 0.1% of 55 ns (4 V Swing, CL = 100 pF)
Slew Rate 135 V/ms (4 V Swing)
–3 dB Bandwidth 60 MHz
Fixed Gain Resistors for High DC Accuracy
Low Voltage Offset 0.5 mV RTO Typical
Gain Error Less than 0.05%
Low Supply Current 3.4 mA
Nominal +12 V Supply
14-Lead SOIC Package
APPLICATIONS
LCD Source Drivers
CD DVD
CDRFigure 1.4 V Step Response
AD8026–SPECIFICATIONSNOISE/DISTORTION PERFORMANCE
INPUT CHARACTERISTICS
OUTPUT CHARACTERISTICS
POWER SUPPLY
NOTESIncludes gain resistor thermal noise.RTO offset includes effects of input voltage offset, input current, and input offset current.Measured in the inverting mode.Observe Absolute Maximum Ratings.
Specifications subject to change without notice.
(@ +258C, VS = 66 V, RI = 500 V, RL = 10 kV, RF = 5K, RG = 3K Noninverting
Configuration, TMIN = 08C, TMAX = +708C, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1Supply␣Voltage VCC–VEE . . . . . . . . . . . . . . . . . . . . . . . 14.0␣V
Internal␣Power␣Dissipation2Small␣Outline␣Package (R) . . . . . . . . . . . . . . . . . . . . 0.9␣W
+Input Voltage VCC–VIN+ . . . . . . . . . . . . . . . . . . . . . .< 12 V
–Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .< VEE + 12 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .> VEE – 12 V
Output Short Circuit Duration␣ . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . . . 0°C to +70°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Specification is for device in free air:
14-Lead SOIC Package: θJA = 120°C/W, where PD = (TJ – TA)/θJA.
MAXIMUM POWER DISSIPATIONThe maximum power that can be safely dissipated by the
AD8026 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition tem-
perature of the plastic, approximately +150°C. Exceeding this
limit temporarily may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
While the AD8026 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
Figure 2.Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8026 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
AD8026–Typical Performance Characteristics
FREQUENCY – Hz
100k500M1M10M100M
NORMALIZED FLATNESS – dB
NORMALIZED OUTPUT – dBFigure 3.Small Signal Bandwidth and 0.1dB Flatness
Figure 4.100 mV Step Response
0.1%
/DIV
TIME – ns20406080100120140160180Figure 5.Short-Term Settling Time
OUTPUT – dBmFigure 6.Large Signal Bandwidth
NORMALIZED OUTPUT – dBFigure 7.Cap Load vs. Frequency
Figure 8.Crosstalk (Output-to-Output) vs. Frequency
IRE34567891011
DIFF PHASE – Degrees0.02
DIFF GAIN – %
IRE34567891011
–0.03Figure 9.Differential Gain and Differential Phase
Figure 10.VOS RTO vs. Temperature
GAIN ACCURACY – %
TEMPERATURE – 8C254055700Figure 11.Gain Accuracy vs. Temperature
Figure 12.Noise (RTO) vs. Frequency
Figure 13.Total Harmonic Distortion
Figure 14.PSRR vs. Frequency
AD8026
FREQUENCY – Hz
10k100M100k1M10M
OUTPUT IMPEDANCE – Figure 15.Output Impedance vs. Frequency
FREQUENCY – Hz
10k100M100k1M10M
10k
INPUT IMPEDANCE –
100kFigure 16.Input Impedance vs. Frequency
FREQUENCY – Hz
NORMALIZED OUTPUT – dB
100k1M10M100M500MFigure 17.Bandwidth and Flatness vs. Series Resistance
into 100 pF
THEORY OF OPERATIONThe AD8026, a quad voltage feedback amplifier with rail-to-rail
output swing, is internally configured for a gain of either –5/3 or
+8/3. The gain-setting resistors are laser trimmed for precise
control of their ratio. In addition, the amplifier’s frequency
response has been adjusted to compensate for the parasitic
capacitances associated with the gain resistors and with the
amplifier’s inverting input. The result is an amplifier with very
tight control of closed-loop gain and settling time.
The amplifier’s input stage will operate with voltages from about
–0.2 V below the negative supply voltage to within about 1V of
the positive supply. Exceeding these values will not cause phase
reversal at the output; however, the input ESD protection de-
vices will begin to conduct if the input voltages exceed the sup-
ply rails by greater than 0.5V. The gain resistors that connect to
Pins 2, 6, 9, and 13 are protected from ESD in such a way that
the voltages applied to these pins may exceed the negative sup-
ply by as much as –7 V.
The rail-to-rail output range of the AD8026 is provided by a
complementary common-emitter output stage. The chosen
circuit topology allows the outputs to source and sink 50mA of
output current and, with the use of an external series resistor, to
achieve rapid settling time while driving capacitive loads within
0.5V of the supply rails.
Output Referred Offset VoltageThe output referred offset voltage for a voltage feedback ampli-
fier can be estimated with the following equation:
where:
VOOS = output referred offset voltage,
VIOS = input referred offset voltage,
IOS = difference of the two input currents,
IB = average of the two input currents,
RP = total resistance in series with positive input,
RF = 5 kΩ, RG = 3 kΩ for this part.
This equation leads to the well known conclusion that, for a
voltage feedback amplifier to maintain minimum output offset
voltage, the value of RP should be selected to match the parallel
combination of RF and RG. It should be noted that the AD8026
was designed for an assumed source impedance, of 500 Ω driv-
ing the +Input. Therefore, the value of RP included on the chip
is 500 Ω less than the ideal value for minimum output offset.
Additional resistance may be added externally, in series with the
+Input, if the part is to be driven by a lower impedance source.
APPLICATIONSThe AD8026 is designed with on-chip resistors for each op amp
to provide accurate fixed gain and low output-referenced offset
voltages. This can result in significant cost and board-space savings
for systems that can take advantage of the AD8026 specifications.
The part is actually trimmed in three steps. First, the supply
current of the part is trimmed. Then the gain is accurately
trimmed to specification. This trim adjusts the values of either
the gain or feedback resistor for a ratio of 5 to 3. The final trim
