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AD7849AR-AD7849BN-AD7849BR-AD7849BR.-AD7849CR
Serial Input, 14-Bit/16-Bit DAC
REV.B
Serial Input,
14-Bit/16-Bit DAC
FEATURES
14-Bit/16-Bit Multiplying DAC
Guaranteed Monotonicity
Output Control on Power-Up and Power-Down
Internal or External Control
Versatile Serial Interface
DAC Clears to 0 V in Both Unipolar and Bipolar Output
Ranges
APPLICATIONS
Industrial Process Control
PC Analog I/O Boards
Instrumentation
GENERAL DESCRIPTIONThe AD7849 is a 14-bit/16-bit serial input multiplying DAC.
The DAC architecture ensures excellent differential linearity
performance, and monotonicity is guaranteed to 14 bits for the
A grade and to 16 bits for all other grades over the specified
temperature ranges.
During power-up and power-down sequences (when the supply
voltages are changing), the VOUT pin is clamped to 0 V via a low
impedance path. To prevent the output of A3 being shorted to
0 V during this time, transmission gate G1 is also opened.
These conditions are maintained until the power supplies
stabilize and a valid word is written to the DAC register. At this
time, G2 opens and G1 closes. Both transmission gates are also
externally controllable via the Reset In (RST IN) control input.
For instance, if the RST IN input is driven from a battery super-
visor chip, then on power-off or during a brown out, the RST
IN input will be driven low to open G1 and close G2. The DAC
must be reloaded, with RST IN high, to re-enable the output.
Conversely, the on-chip voltage detector output (RST OUT) is
also available to the user to control other parts of the system.
FUNCTIONAL BLOCK DIAGRAM
VDDVCC
AD7849
ROFS
RST IN
VOUT
AGND
RST OUT
SDINSCLKSYNCCLRBIN/
COMP
DCENSDOUTLDACVSSDGND
VREF+
VREF–The AD7849 has a versatile serial interface structure and can be
controlled over three lines to facilitate opto-isolator applications.
SDOUT is the output of the on-chip shift register and can be
used in a daisy-chain fashion to program devices in the multi-
channel system. The DCEN (Daisy Chain Enable) input con-
trols this function.
The BIN/COMP pin sets the DAC coding; with BIN/COMP
set to 0, the coding is straight binary; and with it set to 1, the
coding is 2s complement. This allows the user to reset the DAC
to 0 V in both the unipolar and bipolar output ranges.
The part is available in a 20-lead DIP and 20-lead SOIC package.
*. Patent No. 5,319,371.
BIPOLAR OUTPUT
REFERENCE INPUT
OUTPUT CHARACTERISTICS
DIGITAL INPUTS
DIGITAL OUTPUTS
NOTES
AD7849–SPECIFICATIONS1
(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V; VOUT loaded with 2 kΩ,2 200 pF to 0 V; VREF+ = +5 V;
ROFS connected to 0 V; TA = TMIN to TMAX, unless otherwise noted)
NOTES
AD7849
RESET SPECIFICATIONS(These specifications apply when the device goes into the Reset mode during a power-up or
power-down sequence.) VOUT unloaded.VC, Low Threshold Voltage for VCC
NOTESA pull-down resistor (65 kΩ) on VOUT maintains 0 V output when VDD/VSS is below VA.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2(VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V;
RL = 2 kΩ, CL = 200 pF. All Specifications TMIN to TMAX unless otherwise noted.)
AC PERFORMANCE CHARACTERISTICS(These characteristics are included for Design Guidance and are not
subjecttotest.(VREF+= +5V; VDD=+14.25Vto+15.75V;VSS=–14.25Vto–15.75V;VCC=+4.75Vto+5.25V;ROFSconnectedto0V.)NOTESLDAC = 0. Settling time does not include deglitching time of 5 µs (typ).
Specification subject to change without notice.
AD7849
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.4 V to +17 V
VCC to DGND2 . . . . . . . . . . . . . . . . . .–0.4 V, VDD + 0.4 V or
+7 V (Whichever Is Lower)
VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.4 V to –17 V
VREF+ to DGND . . . . . . . . . . . . . . . .VDD + 0.4 V, VSS – 0.4 V
VREF– to DGND . . . . . . . . . . . . . . . .VDD + 0.4 V, VSS – 0.4 V
VOUT to DGND3 . . . . . . . . . . . . . .VDD + 0.4 V, VSS – 0.4 V or
±10 V (Whichever Is Lower)
ROFS to DGND . . . . . . . . . . . . . . . . .VDD + 0.4 V, VSS – 0.4 V
Digital Input Voltage to DGND . . . . . .–0.4 V to VCC + 0.4 V
Input Current to any Pin Except Supplies4 . . . . . . . . .±10 mA
Operating Temperature Range
Commercial/Industrial (A, B, C Versions). . . .–40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . .102°C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . .+260°C
SOP Package, Power Dissipation . . . . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .74°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . .875 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .71°C/W
Lead Temperature, Soldering (Soldering 10 secs) . . .260°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.VCC must not exceed VDD by more than 0.4 V. If it is possible for this to happen
during power-up or power-down (for example, if VCC is greater than +0.4 V while
VDD is still 0 V), the following diode protection scheme will ensure protection.VOUT may be shorted to DGND, +10 V, –10 V, provided that the power dissipation
of the package is not exceeded.Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7849 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*N = Plastic DIP; R = SOP (Small Outline Package); Q = Cerdip.
PIN CONFIGURATION
TERMINOLOGY
Least Significant BitThis is the analog weighting of 1 bit of the digital word in a DAC.
For the AD7849, B, C and T versions, 1 LSB = (VREF+–VREF–)/16. For the AD7849, A version, 1 LSB = (VREF+ – VREF–)/214.
Relative AccuracyRelative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., offset and gain errors are ad-
justed out) and is normally expressed in least significant bits or
as a percentage of full-scale range.
Differential NonlinearityDifferential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of less than ±1 LSB over the
operating temperature range ensures monotonicity.
Gain ErrorGain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer.
Offset ErrorThis is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
Bipolar Zero ErrorWhen the AD7849 is connected for bipolar output and
(100...000) is loaded to the DAC, the deviation of the analog
output from the ideal midscale of 0 V, is called the bipolar zero
error.
Digital-to-Analog Glitch ImpulseThis is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is nor-
mally specified as the area of the glitch in nV-secs.
Multiplying Feedthrough ErrorThis is an ac error due to capacitive feedthrough from either of
the VREF terminals to VOUT when the DAC is loaded with all 0s.
Digital FeedthroughWhen the DAC is not selected (SYNC is held high), high fre-
quency logic activity on the digital inputs is capacitively coupled
through the device to show up as noise on the VOUT pin. This
noise is digital feedthrough.
PIN FUNCTION DESCRIPTIONAD7849
Typical Performance CurvesFigure 1a.AC Feedthrough
Figure 2a.Digital-to-Analog Glitch Impulse Without
Internal Deglitcher
FREQUENCY – Hz
OUT
V pk-pk
FREQUENCY – Hz
OUT
mV pk-pk
104105Figure 1b.AC Feedthrough vs. Frequency
Figure 2b.Digital-to-Analog Glitch Impulse with
Internal Deglitcher
VOUT
CH2 20.0VM 2.5µsCH1 –400mVCH1 10.0V
VREF+
C1 Pk-Pk
10.4V
C2 Pk-Pk
20.8V
C2 RISE
2.79230µs
C2 FALL
3.20385µs
Figure 5.Pulse Response (Small Signal)
Figure 6.Typical Integral Nonlinearity vs. Supplies
VDD/VSS – Volts
DNL
LSB14
0.125Figure 7.Typical Differential Nonlinearity vs. Supplies
Figure 8.Turn-On Characteristics
Figure 9.Turn-Off Characteristics
AD7849Figure 11.AD7849 Output Stage
When the supply voltages are changing, the VOUT pin is clamped
to 0 V via a low impedance path . To prevent the output of A3
being shorted to 0 V during this time, transmission gate G1 is
also opened. These conditions are maintained until the power
supplies stabilize and a valid word is written to the DAC regis-
ter. At this time, G2 opens and G1 closes. Both transmission
gates are also externally controllable via the Reset In (RST IN)
control input. For instance, if the RST IN input is driven from a
battery supervisor chip, then on power-off or during a brown-
out, the RST IN input will be driven low to open G1 and close
G2. The DAC has to be reloaded, with RST IN high, to re-en-
able the output. Conversely, the on-chip voltage detector out-
put (RST OUT) is also available to the user to control other
parts of the system.
The AD7849 output buffer is configured as a track-and-hold
amplifier. Although normally tracking its input, this amplifier is
placed in a hold mode for approximately 5 µs after the leading
edge of LDAC. This short state keeps the DAC output at its
previous voltage while the AD7849 is internally changing to its
new value. So, any glitches that occur in the transition are not
seen at the output. In systems where the LDAC is permanently
low, the deglitching will not be in operation.
CIRCUIT DESCRIPTION
D/A CONVERSIONFigure 10 shows the D/A section of the AD7849. There are
three on-chip DACs each of which has its own buffer amplifier.
DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor
string but have their own analog multiplexers. The voltage ref-
erence is applied to the resistor string. DAC3 is a 12-bit voltage
mode DAC with its own output stage.
The 4 MSBs of the 16-bit digital input code drive DAC1 and
DAC2 while the 12 LSBs control DAC3. Using DAC1 and
DAC2, the MSBs select a pair of adjacent nodes on the resistor
string and present that voltage to the positive and negative
inputs of DAC3. This DAC interpolates between these two
voltages to produce the analog output voltage.
To prevent nonmonotonicity in the DAC due to amplifier offset
voltages, DAC1 and DAC2 “leap-frog” along the resistor string.
For example, when switching from Segment 1 to Segment 2,
DAC1 switches from the bottom of Segment 1 to the top of
Segment 2 while DAC 2 remains connected to the top of Seg-
ment 1. The code driving DAC3 is automatically comple-
mented to compensate for the inversion of its inputs. This
means that any linearity effects due to amplifier offset voltages
remain unchanged when switching from one segment to the
next and 16-bit monotonicity is ensured if DAC3 is monotonic.
So, 12-bit resistor matching in DAC3 guarantees overall 16-bit
monotonicity. This is much more achievable than the 16-bit
matching which a conventional R-2R structure would have
needed.
Output StageThe output stage of the AD7849 is shown in Figure 11. It is ca-
pable of driving a load of 2 kΩ in parallel with 200 pF. The
feedback and offset resistors allow the output stage to be config-
ured for gains of 1 or 2. Additionally, the offset resistor may be
used to shift the output range.
The AD7849 has a special feature to ensure output stability
during power-up and power-down sequences. This is specifi-
cally available for control applications where actuators must not
be allowed to move in an uncontrolled fashion.
10/12
DAC 3
VREF+
VREF–Figure 10.AD7849 D/A Conversion
