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AD7666AST
16-Bit, 500 kSPS PulSAR® Unipolar ADC with Ref
16-Bit 500 kSPS PulSAR®
Unipolar ADC with Reference
Rev. 0
FEATURES
2.5 V internal reference: typical drift 3 ppm/°C
Guaranteed max drift 15 ppm/°C
Throughput: 500 kSPS
INL: ±2.0 LSB max (±0.0038% of full scale)
16-bit resolution with no missing codes
S/(N+D): 88 dB min @ 20 kHz
THD: –96 dB max @ 20 kHz
Analog input voltage range: 0 V to 2.5 V
Both AC and DC specifications
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPITM/MICROWIRETM/DSP compatible
Single 5 V supply operation
Power dissipation
66 mW typ, 132 µW @ 1 kSPS without REF
81 mW typ with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs
APPLICATIONS
Data acquisition
Medical instruments
Digital signal processing
Spectrum analysis
Instrumentation
Battery-powered systems
Process control
GENERAL DESCRIPTION The AD7666* is a 16-bit, 500 kSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed, 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter-
face ports. The AD7666 is hardware factory-calibrated and
comprehensively tested to ensure ac parameters such as signal-
to-noise ratio (SNR) and total harmonic distortion (THD), in
addition to the more traditional dc parameters of gain, offset,
and linearity.
The AD7666 is available in a 48-lead LQFP and a tiny 48-lead
LFCSP, with operation specified from –40°C to +85°C. Patent Pending.
FUNCTIONAL BLOCK DIAGRAM DATA[15:0]
BUSY
SER/PAR
OB/2C
OGND
OVDD
DGNDDVDD
AVDD
AGND
REFREFGND
INGND
RESET
CNVST
REFBUFIN
PDBUF
PDREF
BYTESWAP
Figure 1. Functional Block Diagram
Table 1. PulSAR Selection
PRODUCT HIGHLIGHTS 1. Fast Throughput.
The AD7666 is a 500 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL.
The AD7666 has a maximum integral nonlinearity of
2.0 LSB with no missing 16-bit codes.
3. Internal Reference.
The AD7666 has an internal reference with a typical
temperature drift of 3 ppm/°C.
4. Single-Supply Operation.
The AD7666 operates from a single 5 V supply. Its power
dissipation decreases with throughput.
5. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
TABLE OF CONTENTS Specifications.....................................................................................3
Timing Specifications.......................................................................5
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Definitions of Specifications.........................................................11
Typical Performance Characteristics...........................................12
Circuit Information........................................................................16
Converter Operation..................................................................16
Typical Connection Diagram...................................................18
Power Dissipation versus Throughput....................................20
Conversion Control....................................................................21
Digital Interface..........................................................................22
Parallel Interface.........................................................................22
Serial Interface............................................................................22
Master Serial Interface...............................................................23
Slave Serial Interface..................................................................24
Microprocessor Interfacing.......................................................26
Application Hints...........................................................................27
Bipolar and Wider Input Ranges..............................................27
Layout..........................................................................................27
Evaluating the AD7666’s Performance....................................27
Outline Dimensions.......................................................................28
Ordering Guide..........................................................................28
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted See An section. alog InputLSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV. See the De section. These specifications do not include the error contribution from the external reference. finitions of Specifications
4All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. Parallel or Serial 16-Bit.
6Conversion results are available immediately after completed conversion. The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8 With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH. With PDREF, PDBUF LOW and PD HIGH.
10 Tested in parallel reading mode. Consult factory for extended temperature range.
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted In serial interface mode, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In serial master read during convert mode. See Table 4 for serial master read after convert mode.
Table 4. Serial Clock Timings in Master Read after Convert ABSOLUTE MAXIMUM RATINGS
Table 5. AD7666 Stress Ratings1 Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability. See Analog Input section.
3 See the Voltage Reference Input section. Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.
500µA
1.6mA
TO OUTPUTPIN1.4V
60pF*
*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.03033-0-002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs CL = 10 pF
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this product features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND
CNVST
RESET
DGND
AGND
AVDD
BYTESWAP
OB/2C
NC = NO CONNECT
SER/PAR
BUSY
D15
D14
D13
D3/DIVSCLK1D12
/INT
/IN
VSYN
D6/INVSCL
/RDC/S
OGNDOVDD
DGND
DOUT
10/SYN
/RDE
RROR
DBUF
DRE
FBUFIN
TEMPAVAGNDAGNDNCINGNDRE
FGNDD2/DIVSCLK0
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Full-Scale Error The last transition (from 011…10 to 011…11 in twos
complement coding) should occur for an analog voltage 1½ LSB
below the nominal full scale (2.49994278 V for the 0 V to 2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.
Unipolar Zero Error The first transition should occur at a level ½ LSB above analog
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero
error is the deviation of the actual transition from that point.
Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number Of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) and is expressed in bits by the
following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response Transient response is the time required for the AD7666 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the
maximum and minimum reference output voltage (VREF)
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C
using the following equation: 10)–()25(–))/(××°=°
MINMAXREF
REFREFREFTTVV(VCppmTCVC
MinMax
where:
VREF(Max) = Maximum VREF at TMIN, T(25°C), or TMAX
VREF(Min) = Minimum VREF at TMIN, T(25°C), or TMAX
VREF(25°C) = VREF at +25°C
TMAX = +85°C
TMIN = –40°C
Thermal Hysteresis Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS+ = +25°C to TMAX to +25°C
T_HYS– = +25°C to TMIN to +25°C
It is expressed in ppm using the following equation: 10)25(_()25()(×°°=CV
HYSTVCVppmV
REF
REFREF
HYS
where:
VREF(25°C) = VREF at 25°C
VREF(T_HYS) = Maximum change of VREF at T_HYS+ or
T_HYS–.
TYPICAL PERFORMANCE CHARACTERISTICS INL (
SB)16384327684915265536
CODE
Figure 5. Integral Nonlinearity vs. Code
POSITIVE INL (LSB)
NUMBE
R OF UNITS
Figure 6. Typical Positive INL Distribution (99 Units)
NUMBE
R OF UNITS0.250.500.751.001.251.50
POSITIVE DNL (LSB)
Figure 7. Typical Positive DNL Distribution (99 Units)
CODE
DNL (LSB)
Figure 8. Differential Nonlinearity vs. Code
NEGATIVE INL (LSB)
NUMBER OF UNITS
Figure 9. Typical Negative INL Distribution (99 Units)
NEGATIVE DNL (LSB)
NUMBER OF UNITS
Figure 10. Typical Negative DNL Distribution (99 Units)
COUNTS
7FFE7FFF80008001800280037FFD8004
CODE IN HEX
7FFC
Figure 11. Histogram of 261,120 Conversions of a
DC Input at the Code Transition
AMPLITUDE (dB of Full Sc50100150200250
FREQUENCY (kHz)
Figure 12. FFT Plot
SNR, S/[N+D] (dB)101001000
FREQUENCY (kHz)
ENOB (Bits)
Figure 13. SNR, S/(N+D), and ENOB vs. Frequency
COUNTS
CODE IN HEX
7FFA7FFB7FFC7FFD7FFE7FFF800080018002
Figure 14. Histogram of 261,120 Conversions of a
DC Input at the Code Center
THD, HARMONICS (dB)101001000
FREQUENCY (kHz)
SFDR (dB)
Figure 15. THD, Harmonics, and SFDR vs. Frequency
INPUT LEVEL (dB)
SNR, S/[N+D] REFERRE
D TO FULL-SCALE (dB)
Figure 16. SNR and S/(N+D) vs. Input Level (Referred to Full Scale)
ENOB (
NR,
/[N+D] (dB)
TEMPERATURE (°C)
Figure 17. SNR, S/(N+D), and ENOB vs. Temperature
TEMPERATURE (°C)
THD, HARMONICS
(dB)
Figure 18. THD and Harmonics vs. Temperature
1000001001k10k100k1M
SAMPLING RATE (SPS)
RATING CURRE
NTS
(
Figure 19. Operating Current vs. Sample Rate
RO E
RROR, FULL-S
CALE
RROR (LS
TEMPERATURE (°C)
Figure 20. Zero Error, Full-Scale Error without Reference vs. Temperature
TEMPERATURE (°C)
EF (
Figure 21.Typical Reference Voltage Output vs. Temperature (2 Units)
NUMBE
R OF UNITS0.51.01.52.02.53.03.54.04.55.05.56.06.57.0
REFERENCE DRIFT (ppm/°C)
7.58.0
Figure 22. Reference Voltage Temperature Coefficient Distribution (93 Units)
