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AD7572AAR03ADN/a87avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AJN03N/a30avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AJN10ADIN/a554avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AJN10ADN/a279avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AJN10N/a19avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AJR/10 |AD7572AJR10ADN/a79avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AJR03ADN/a30avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AJR10ADN/a207avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572ALN03N/a5avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AAN03ADN/a20avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
AD7572AAN10N/a7avaiLC2MOS COMPLETE, HIGH SPEED 12-BIT ADC


AD7572AJN10 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCspecifications over the original AD7572. The AD7572A is a complete 12-bit ADC that offers high ..
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AD7572AJR/10 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCSpecifications subject to change without notice. REV. AAD7572A TIMING tyiNtNyrERIsmsl (IG, = ..
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AD7572AJR10 ,LC2MOS COMPLETE, HIGH SPEED 12-BIT ADCANALOG DEVICES Limos Complete, High Speed 12-Bit Mil AD7572A
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AD7572AAN03-AD7572AAN10-AD7572AAR03-AD7572AJN03-AD7572AJN10-AD7572AJR/10-AD7572AJR03-AD7572AJR10-AD7572ALN03
LC2MOS COMPLETE, HIGH SPEED 12-BIT ADC
ANALOG
DEVICES
Complete, High Speed 12-Bit ADC
AD7572A
FEATURES
Improved AD7572
Faster Conversion Time
AD7572AXX03: 3 pts
AD7572AXX10: 10 ps
5 V and -12 V or -15 V Power Supply Operation
Better Offset and Gain Error Specifications
Extended Plastic Temperature Range
(-400C to +85°C)
Low Power: 100 mW
Small 24-Pin, 0.3" Wide DIP and
SOIC DIP Packages
GENERAL DESCRIPTION
The AD7572A is an enhanced replacement for the industry stan-
dard AD7572. Improvements include faster conversion times of
3 us for the AD7572AXX03 and 10 ILS for the AD7572AXX10.
The required power supplies are 5 V and -12 V or - 15 V. Ad-
ditional features are better offset and gain error specifications
over the original AD7572.
The AD7572A is a complete 12-bit ADC that offers high speed
performance combined with low, CMOS power levels. The part
uses an accurate, high speed DAC and comparator in a
successive-approximation loop to achieve a fast conversion time.
An on-chip buried Zener diode provides a stable reference volt-
age to give low drift performance over the full temperature
range and the specified accuracy is achieved without any user
trims. An on-chip clock circuit is provided, which may be used
with a crystal for stand-alone operation, or the clock input may
be driven from an external clock source such as a divided-down
microprocessor clock. The only other external components re-
quired for basic operation of the AD7572A are decoupling ca-
pacitors for the supply voltages and reference output.
The AD7572A has a high speed digital interface with three-state
data outputs and can operate under the control of standard mi-
croprocessor Read (ICD) and decoded address ((3) signals. In-
terface timing is sufficiently fast to allow the AD7572A to
operate with most microprocessors, with three-state enable times
of only 90 ns and bus relinquish times of 75 ns.
The AD7572A is fabricated in Analog Devices Linear Compati-
ble CMOS process (LCZMOS), an advanced all ion-implanted
process that combines fast CMOS logic and linear, bipolar cir-
cuits on a single chip, thus achieving excellent linear perfor-
mance while retaining low CMOS power levels.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
AGND '
12-BIT DAC
BURIED
REFERENCE
SUCCESSIVE
APPROXIMA'IION
REGISTER
AD7572A
" BIT LATCH
22 BUST
21 (T5
CONTROL
MULTlPLExER " HEEN
THREE-STATE THREE-STATE CLOCK " Cu out
DUTPUT OUTPUT OSCILLATOR
DRIVERS DRIVERS " CLK IN
.-tlrd---olicd CE en
DH 08 D7 D4 DGND 0311 DD!
PRODUCT HIGHLIGHTS
1. Fast Conversion Time
Fast, 3 us and 10 pts conversion times make the AD7572A
ideal for DSP applications and wideband data acquisition
systems.
2. Wide Power Supply Range
The AD7572A operates from S V and - 12 V or - 15 V
power supplies.
3. Microprocessor Interface
Fast, easy-to-use digital interface has three-state bus access
times of 90 ns and bus relinquish times of 75 ns allowing the
AD7572A to interface to most microprocessors.
4. Low Power
LCZMOS circuitry gives low power drain (100 mW) from
+5, - 12 volt supplies.
5. 24-pin 0.3" DIP and SOIC packages offer space saving over
parts in 28-pin 0.6" DIP.
One Technology Way, PO. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 61 71329-4700 Fax: 617/326-8703 wa: 710/394-6577
Telex: 924491 Cable: ANALOG NORWOODMASS
M757n-$PEtlFliyfrl0lG
(h, = +5ll ' 5%, Ilss = -11.0to -ftidi ll, AGND = BEND = " far.
4.0 MHz for AD1572AXX03, 1.25 Mit for A01572AXX10. M Specifications u, to
u, unless otherwise noted. Specifications apply to Slow Memory Mode.)
J, A L S
Parameter Versionsl Version' Version' Units Test Conditions/Comments
ACCURACY
Resolution 12 12 12 Bits
Integral Nonlinearity a 25°C t t 1/2 t LSB max
TM to T,,,,, tl tl/2 tl LSB max
Differential Nonlinearity t tl tl LSB max
Minimum Resolution for Which No
Missing Codes Are Guaranteed 12 12 12 Bits
Offset Error (E 25°C t2 t2 ut2 LSB max
Tu,, to Tm t4 t4 t4 LSB max Typical Change over Temp is tl LSB
Full Scale (FS) Errorz (ii 25°C t8 til. t8 LSB max FS = 5 V
Full Scale TC" q 45 25 45 ppml°C max Ideal Last Code Transition = FS -3/2 LSBs
ANALOG INPUT
Input Voltage Range 0 to +5 0 to +5 0 to +5 Volts For Bipolar Operation See Figures 10
Input Current 3.5 3.5 3.5 mA max and 12
INTERNAL REFERENCE VOLTAGE
VREF Output @ 25°C -5.2/-5.3 -5.2/-5.3 -5.21-5.3 V min/V max -5.25 V tlo/o
VREF Output TC 40 20 40 ppml°C typ External Load Should Not
Output Current Sink Capability 550 550 550 WA max Change During Conversion
POWER SUPPLY REJECTION
G, Only tl/2 tl/2 :1/2 LSB typ FS Change, Vss = -12 V or -15 V
Vor, = 4.5 V to 5.5 V
Vss Only tll tl/2 tll LSB typ FS Change, Vor, = S V
Vss = -11.4 V to -16.5 V
LOGIC INPUTS
' RD, HBEN, CLK IN
VINL, Input Low Voltage +0.8 +0.8 +0.8 V max Vor, = 5 V :5%
VIN", Input High Voltage +2.4 +2.4 +2.4 V min
Cm, Input Capacitance' 10 10 10 pF max
a, m, HBEN
Ino Input Current +10 :10 :10 wh max VIN = 0 V to VDD
CLK IN
lm, Input Current :20 t20 t20 " max Ilu,, = 0 V to VDD
LOGIC OUTPUTS
D11-D0/8, BUSY, CLK OUT
VOL, Output Low Voltage +0.4 +0.4 +0.4 V max Ismx = 1.6 mA
Voss, Output High Voltage +4.0 +4.0 +4.0 V min Isounce = 200 WA
Dll-DO/8
Floating-State Leakage Current :10 t10 :10 WA max
Floating-State Output Capacitance' 15 15 15 pF max
CONVERSION TIME
AD7572AXX03
Synchronous Clock 3.125 3.125 3.125 11s max {CLK = 4 MHz. See Under
Asynchronous Clock 3/3.25 313.25 3/3.25 p.s min/ws max Control Inputs Synchronization
AD7572AXX10
Synchronous Clock 10 10 - us max fCLK = 1.25 MHz
Asynchronous Clock 9.6/10.4 9.6/10.4 - ws min/ws max
POWER REQUIREMENTS
Vor, +5 +5 +5 V nom :5% for Specified Performance
Vss -12 to -15 -12 to -15 -12 to -15 V nom -11.4 V to -16.5 V for Specified Performance
Iraf' 7 7 7 mAmax trs= R-D-- VDD,A1N= 5V V
Iss6 10 10 12 mA max a = W = VDD,A1N = 5 v
Power Dissipation 100 100 120 mW typ Vss = - 12 V
155/185 155/185 179/215 mW max Vss = -12 W-15 V
'Temperature ranges are " follows: J, L Versions, 0 to +70°C; A Version, -40''C to +85°C; S Version, -55°C to + 125°C.
2Includes internal voltage reference error.
Tull-Scale TC = AFS/AT where AFS is Full-Scale change from T, = +25°C to Tmin or T
'Includes internal voltage reference drift.
'Sample tested to ensure compliance.
'Power supply current is measured when the AD7572A is inactive, i.e., tT; = E = BUSY = HIGH.
Specifications subject to change without notice.
REV. A
A07572A
TIMING tyihMimimsTIes1 (IG, = " t 5%, Ilss = -11.4 ll to -16.5 ll)
Limit at +25°c Limit at Tm, Tmax Limit at Tm, Tm,
Parameter (All Grades) (J , L, A Grades) (S Grade) Units Conditions/Comments
t1 0 0 0 ns min E to E Setup Time
tir 190 230 270 ns max E to BUSY Propagation Delay
tsz 90 110 120 ns max Data Access Time after 6, C1,:20 pF
125 150 170 ns max Data Access Time after Ary, CL: 100 pF
t4 ts ts t, ns min E Pulse Width
ts 0 0 0 ns min c-s to R-ry Hold Time
I62 70 90 100 ns max Data Setup Time after BUSY
tr' 15 15 _ 15 ns min Bus Relinquish Time
75 85 90 ns max
te 0 0 0 ns min HBEN to E Setup Time
t9 0 0 0 ns min HBEN to E Hold Time
tlo 200 200 200 ns min Delay Between Successive
Read Operations
"Timing Specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with tr = If - 5 ns (10% to 90% of +5 V) and
timed from a voltage level of 1.6 V.
't, and ts are measured with the load circuits of Figure l and defined as the time required for an output to cross 0.8 V or 2.4 V.
'r, is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
CAUTION:
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subjected to high energy elec-
trostatic fields. Unused devices must be stored in conductive foam or shunts. The foam should
be discharged to the destination socket before devices are removed.
DEM DEM
DGND I
a. High-Z to Vo,, (ta)
and VOL to Vo,, (ts)
I DGND
b. High- to ' (ta)
and Vo,, to VOL (ts)
Figure 1. Load Circuits for Access Time
b. ' to High-Z
DGND I
a. Vor, to High-
Figure 2. Load Circuits for Output Float Delay
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
Vor, to DGND .................... -0.3 V to +7 V
Vss to DGND .................... +0.3Vto -17V
AGND to DGND ............... -0.3 V, VDI) + 0.3 V
AIN to AGND .................... -15Vto +15V
Digital Input Voltage to DGND
(CLK IN, HBEN, E, (E) ....... -0.3 V, Vor, +0.3 V
Digital Output Voltage to DGND
(Dll-DO/8, CLK OUT, BUSY) ..... -0.3 V, Vor, +0.3 V
Operating Temperature Range
Commercial (J, L Versions) .............. 0 to +70°C
Industrial (A Version) ............... -40'C to +85°C
Extended (S Version) .............. -55oC to + 125°C
Storage Temperature ................ -6S'C to + 150°C
Lead T emperature (Soldering, 10 secs) ........... +300°C
Power Dissipation (Any Package) to +75°C ...... 1,000 mW
Derates above +75°C by .................. 10 mW/°C
*Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other condition above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
REV. A
AD7572A
ORDERING GUIDE PIN CONFIGURATION
! Conversion Temperature Full-Scale Accuracy Package V
Model Time Range TC Grade Optionl AIN E q E Voo
AD7572AJN03 3 115 0°C to +70°C 45 ppm/°C tl LSB N-24 vm E E Vss
AD7572AAN03 3 its _ 40°C to +85°C 45 ppm/°C tl LSB N-24 AGND E E m
AD7572ASQ032 3 its -55''C to +125°C 45 ppm/°C tl LSB Q-24 on E E a
AD7572ALN03 3 115 0°C to +70°C 25ppm/°C :1/2 LSB N-24 m E E E
AD7572AAQ03 3 11s -4(y'C to +85°C 45 ppm/°C tl LSB Q-24 AD7572A
AD7572AJR03 3 1115 0°C to +70°C 45 ppm/°C tl LSB R-24 D9 E T0PVIEW CEI HBEN
AD7572AAR03 3 115 -40oC to +85°C 45 ppm/T tl LSB R-24 D8 E (NottoScale) % CLKOUT
AD7572AJN10 10 115 0°C to +70°C 45 ppm/°C tl LSB N-24 D7 E " CLKIN
AD7572AAN10 10 HS -40'C to +85°C 45 ppm/°C tl LSB N-24 " E E m
AD7572ALN10 10 11s 0°C to +70°C 25 ppm/°C t 1/2 LSB N-24 D5 E E W
AD7572AJR10 10 us 0°C to +70°C 45 ppm/°C tl LSB R-24 04 11 E um
NOTES DGND 12 E 0311
1N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
2AD7572ASQ03 will be available to /883B processing only. Contact your local sales office for release
information.
PIN FUNCTION DESCRIPTION
Pin No. Mnemonic Description
1 AIN Analog Input.
2 VREF Voltage Reference Output. The AD7572A has its own internal -5.25 V reference.
3 AGND Analog Ground.
4 . . 11 D11 . . . D4 Three State Data Outputs. They become active when (f and E are brought low.
13 . . 16 D3/11 . . . DO/8 Individual pin function is dependent upon High Byte Enable (HBEN) Input.
DATA BUS OUTPUT, (E & E = LOW
Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* Dll D10 D9 D8 D7 D6 D5 D4 D3/ll D2/10 Dl/9 D0/8
HBEN - LOW DBll D810 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DBI DB0
HBEN = HIGH DBll D310 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8
*Dll . . . D0/8 are the ADC data output pins.
DBll . . . DBO are the 12-bit conversion results, DBll is the MSB.
12 DGND Digital Ground.
17 CLK IN Clock Input Pin. An external TTL compatible clock may be applied to this pin. Alternatively,
a crystal or ceramic resonator may be connected between CLK IN (Pin 17) and CLK OUT
(Pin 18).
18 CLK OUT Clock Output Pin. An inverted CLK IN signal appears at CLK OUT when an external clock is
used. See CLK IN (Pin 17) description for crystal (resonator).
19 HBEN High Byte Enable Input. Its primary function is to multiplex the 12 bits of conversion data onto
the lower D7 . . . D0/8 outputs (4 MSBs or 8 LSBs). See Pin Description 4 . . . 11 and
13 . . . 16. It also disables conversion start when HBEN is high.
20 E READ Input. This active LOW signal, in corenction with (f, is used to enable the output data
three-state drivers and initiate a conversion if CS and HBEN are low.
21 (E CHIP SELECT Input. This active LOW signal, in cor1iunc_tin with E is used to enable the
output data three-state drivers and initiate a conversion if RD and HBEN are low.
22 BUSY BUSY Output indicates converter status. BOSY is LOW during conversion.
23 Vss Negative Supply, - 12 V to -15 V.
24 Voo Positive Supply, +5 V.
REV. A
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