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AD7248AAN ,LC2MOS 12-Bit DACPORTsfeatures include extended temperature rangeDDoperation for commercial and industrial grades.The AD7 ..
AD7248AAN ,LC2MOS 12-Bit DACPORTsCHARACTERISTICS (V = +12 V to +15 V; V = O V or –12 V to –15 V; See Figures 5 and 7.)DD SSParameter ..
AD7248AAP ,LC2MOS 12-Bit DACPORTsfeatures a wide power supply rangeDACPORT is a registered trademark of .allowing operation from 12 ..
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AD7248AAP ,LC2MOS 12-Bit DACPORTsFEATURESAD7245A FUNCTIONAL BLOCK DIAGRAM12-Bit CMOS DAC with Output Amplifier andReferenceImproved ..
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ADD8704ARUZ ,16 V Quad Operational AmplifierGENERAL DESCRIPTION +IN A 2 ADD8704 11 +IN DThe ADD8704 is a single-supply quad operational amplifi ..
ADD8704ARUZ-REEL ,16 V Quad Operational AmplifierCHARACTERISTICS Offset Voltage V 2 15 mV OSOffset Voltage Drift –40°C ≤ T ≤ +85°C 10 µV/° ..
AD7248A
12-Bit DACPORT with Double-Buffered Parallel Input
REV.B
LC2MOS
12-Bit DACPORTs
FEATURES
12-Bit CMOS DAC with Output Amplifier and
Reference
Improved AD7245/AD7248:
12 V to 15 V Operation�1/2 LSB Linearity Grade
Faster Interface—30 ns Typ Data Setup Time
Extended Plastic Temperature Range (–40�C to +85�C)
Single or Dual Supply Operation
Low Power—65 mW Typ in Single Supply
Parallel Loading Structure: AD7245A
(8+4) Loading Structure: AD7248A
GENERAL DESCRIPTIONThe AD7245A/AD7248A is an enhanced version of the industry
standard AD7245/AD7248. Improvements include operation
from 12 V to 15 V supplies, a ±1/2 LSB linearity grade, faster
interface times and better full scale and reference variations with
VDD. Additional features include extended temperature range
operation for commercial and industrial grades.
The AD7245A/AD7248A is a complete, 12-bit, voltage output,
digital-to-analog converter with output amplifier and Zener voltage
reference on a monolithic CMOS chip. No external user trims
are required to achieve full specified performance.
Both parts are microprocessor compatible, with high speed data
latches and double-buffered interface logic. The AD7245A accepts
12-bit parallel data that is loaded into the input latch on the
rising edge of CS or WR. The AD7248A has an 8-bit-wide data
bus with data loaded to the input latch in two write operations.
For both parts, an asynchronous LDAC signal transfers data
from the input latch to the DAC latch and updates the analog
output. The AD7245A also has a CLR signal on the DAC latch
which allows features such as power-on reset to be implemented.
The on-chip 5 V buried Zener diode provides a low noise, tem-
perature compensated reference for the DAC. For single supply
operation, two output ranges of 0 V to 5 V and 0 V to 10 V are
available, while these two ranges plus an additional ±5 V range
are available with dual supplies. The output amplifiers are capa-
ble of developing 10 V across a 2 kΩ load to GND.
The AD7245A/AD7248A is fabricated in linear compatible CMOS
(LC2MOS), an advanced, mixed technology process that combines
precision bipolar circuits with low power CMOS logic. The
AD7245A is available in a small, 0.3" wide, 24-lead DIP and
SOIC and in 28-terminal surface mount packages. The AD7248A
is packaged in a small, 0.3" wide, 20-lead DIP and SOIC and in
20-terminal surface mount packages.
DACPORT is a registered trademark of Analog Devices, Inc.
AD7245A FUNCTIONAL BLOCK DIAGRAM
AD7248A FUNCTIONAL BLOCK DIAGRAM
DB7DB0DGND
VSS
CSMSB
CSLSB
LDAC
AGND
VDDREF OUTROFS
RFB
VOUT
PRODUCT HIGHLIGHTS1. The AD7245A/AD7248A is a 12-bit DACPORT® on a single
chip. This single chip design and small package size offer
considerable space saving and increased reliability over
multichip designs.
2. The improved interface times on the part allows easy, direct
interfacing to most modern microprocessors.
3. The AD7245A/AD7248A features a wide power supply range
allowing operation from 12 V supplies.
REFERENCE OUTPUT
DIGITAL INPUTS
ANALOG OUTPUTS
POWER REQUIREMENTS
NOTESPower supply tolerance is ±10%.Temperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version;–55°C to +125°C.See Terminology.With appropriate power supply tolerances.FSR means Full-Scale Range and is 5 V for the 0 V to 5 V output range and 10 V for both the 0 V to 10 V and ±5 V output ranges.This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.This error is calculated with respect to an ideal 4.9988 V on the 0 V to 5 V and ±5 V ranges; it is calculated with respect to an ideal 9.9976 V on the 0 V to 10 V
range. It includes the effects of internal voltage reference, gain and offset errors.Full-Scale TC = ∆FS/∆T, where ∆FS is the full-scale change from TA = 25°C to TMIN or TMAX.Guaranteed by design and characterization, not production tested.0 V to 10 V output range is available only when VDD ≥ +14.25 V.
Specifications subject to change without notice.
AD7245A/AD7248A–SPECIFICATIONS
(VDD = +12 V to +15 V,1 VSS = O V or –12 V to –15 V,1
AGND = DGND = O V, RL = 2 k�, CL = 100 pF. All specifications TMIN to TMAX unless otherwise noted.)
SWITCHING CHARACTERISTICS1NOTESSample tested at 25°C to ensure compliance.Power supply tolerance is ±10%.
ABSOLUTE MAXIMUM RATINGS1VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
VOUT to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 24 V
VOUT to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –32 V, 0 V
REF OUT2 to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Power Dissipation (Any Package) to 75°C . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2The output may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. VOUT short circuit current is typically
80 mA.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
(VDD = +12 V to +15 V;2 VSS = 0 V to –12 V to –15 V;2 See Figures 5 and 7.)
AD7245A/AD7248A
DAC GAIN ERRORDAC Gain Error is a measure of the output error between an
ideal DAC and the actual device output with all 1s loaded after
offset error has been allowed for. It is, therefore defined as:
Measured Value—Offset—Ideal Value
where the ideal value is calculated relative to the actual refer-
ence value.
UNIPOLAR OFFSET ERRORUnipolar Offset Error is a combination of the offset errors of the
voltage mode DAC and the output amplifier and is measured
when the part is configured for unipolar outputs. It is present
for all codes and is measured with all 0s in the DAC register.
BIPOLAR ZERO OFFSET ERRORBipolar Zero Offset Error is measured when the part is config-
ured for bipolar output and is a combination of errors from the
DAC and output amplifier. It is present for all codes and is
measured with a code of 2048 (decimal) in the DAC register.
SINGLE SUPPLY LINEARITY AND GAIN ERRORThe output amplifier of the AD7245A/AD7248A can have a
true negative offset even when the part is operated from a single
positive power supply. However, because the lower supply rail
to the part is 0 V, the output voltage cannot actually go nega-
tive. Instead the output voltage sits on the lower rail and this
results in the transfer function shown. This is an offset effect
and the transfer function would have followed the dotted line if
the output voltage could have gone negative. Normally, linearity
is measured after offset and full scale have been adjusted or
allowed for. On the AD7245A/AD7248A the negative offset is
allowed for by calculating the linearity from the code which the
amplifier comes off the lower rail. This code is given by the
negative offset specification. For example, the single supply
linearity specification applies between Code 3 and Code 4095
for the 25°C specification and between Code 5 and Code 4095
over the TMIN to TMAX temperature range. Since gain error is
also measured after offset has been allowed for, it is calculated
between the same codes as the linearity error. Bipolar linearity and
gain error are measured between Code 0 and Code 4095.
NEGATIVE
OFFSET
OUTPUT
VOLTAGE
TERMINOLOGY
RELATIVE ACCURACYRelative Accuracy, or endpoint nonlinearity, is a measure of the
actual deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after allowing for
zero and full scale and is normally expressed in LSBs or as a
percentage of full-scale reading.
DIFFERENTIAL NONLINEARITYDifferential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
DIGITAL FEEDTHROUGHDigital Feedthrough is the glitch impulse injected from the digital
inputs to the analog output when the inputs change state. It is
measured with LDAC high and is specified in nV-s.
AD7245A ORDERING GUIDENOTESTo order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.This grade will be available to /883B processing only.
AD7248A ORDERING GUIDENOTESTo order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.This grade will be available to /883B processing only.
AD7245A PIN FUNCTION DESCRIPTIONS
(DIP PIN NUMBERS)
AD7245A PIN CONFIGURATIONS
DIP and SOIC
LCCC321282726131415161718
AGND
DB11
DB10
DB9
DB8
DB7
DB6DB5
DGND
DB4DB3DB2
CLR
LDAC
DB0
DB1
REF OUTR
OFSV
OUT
NC = NO CONNECT
PLCC
AGND
DB11
DB10
DB9
DB8
DB7DB1
DB0
LDAC
CLR
DB2DB3DB4
DGND
DB5DB6
OUT
OFS
REF OUT
NC = NO CONNECT
AD7245A/AD7248A
AD7248A PIN FUNCTION DESCRIPTIONS
(ANY PACKAGE) 2
3
4
5
6
7
8
9
AD7248A PIN CONFIGURATIONS
DIP and SOIC
LCCC2
AGND
(MSB) DB7
DB6
DB5
DB4CSMSB
CSLSB
LDAC
VDD
OUT
OFS
REF OUT
(LSB) DB0
DB1DB2
DGND
DB3
PLCC
AGND
(MSB) DB7
DB6
DB5
DB4CSMSB
CSLSB
LDAC
VDD
OUT
OFS
REF OUT
(LSB) DB0
DB1
DB2
DGND
DB3
TPC 1.Power Supply Current vs. Temperature
TPC 2.Noise Spectral Density vs. Frequency
TPC 3. Positive-Going Settling Time
(VDD = +15 V, VSS = –15 V)
TPC 4.Reference Voltage vs. Temperature
TPC 5.Power Supply Rejection Ration vs. Frequency
TPC 6. Negative Going Settling Time
(VDD = +15 V, VSS = –15 V)
AD7245A/AD7248A
CIRCUIT INFORMATION
D/A SECTIONThe AD7245A/AD7248A contains a 12-bit voltage mode digi-
tal-to-analog converter. The output voltage from the converter
has the same positive polarity as the reference voltage allowing
single supply operation. The reference voltage for the DAC is
provided by an on-chip buried Zener diode.
The DAC consists of a highly stable, thin-film, R–2R ladder and
twelve high-speed NMOS single-pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in Figure 1.
RRRR2R2R2R2R2RDB9DB10DB11
VOUT
RFB2RROFS
AGND
VREF
SHOWN FOR ALL 1s ON DACFigure 1.D/A Simplified Circuit Diagram
The input impedance of the DAC is code dependent and can
vary from 8 kΩ to infinity. The input capacitance also varies
with code, typically from 50 pF to 200 pF.
OP AMP SECTIONThe output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The user has access to two gain
setting resistors which can be connected to allow different out-
put voltage ranges (discussed later). The buffer amplifier is
capable of developing up to 10 V across a 2 kΩ load to GND.
The output amplifier can be operated from a single positive
power supply by tying VSS = AGND = 0 V. The amplifier can
also be operated from dual supplies to allow a bipolar output
range of –5 V to +5 V. The advantages of having dual supplies
for the unipolar output ranges are faster settling time to voltages
near 0 V, full sink capability of 2.5 mA maintained over the entire
output range and elimination of the effects of negative offset on
the transfer characteristic (outlined previously). Figure 2 shows
the sink capability of the amplifier for single supply operation.
The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 25 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier has a typical peak-to-
peak figure of 150 µV for a 1 MHz output bandwidth. There is
no significant difference in the output noise between single and
dual supply operation.
VOLTAGE REFERENCEThe AD7245A/AD7248A contains an internal low noise buried
Zener diode reference which is trimmed for absolute accuracy
and temperature coefficient. The reference is internally connected
to the DAC. Since the DAC has a variable input impedance at
its reference input the Zener diode reference is buffered. This
buffered reference is available to the user to drive the circuitry
required for bipolar output ranges. It can be used as a reference
for other parts in the system provided it is externally buffered.
The reference will give long-term stability comparable with the
best discrete Zener reference diodes. The performance of the
AD7245A/AD7248A is specified with internal reference, and all
the testing and trimming is done with this reference. The reference
should be decoupled at the REF OUT pin and recommended
decoupling components are 10 µF and 0.1 µF capacitors in
series with a 10 Ω resistor. A simplified schematic of the refer-
ence circuitry is shown in Figure 3.
Figure 3.Internal Reference
DIGITAL SECTIONThe AD7245A/AD7248A digital inputs are compatible with
either TTL or 5 V CMOS levels. All data inputs are static pro-
tected MOS gates with typical input currents of less than 1 nA.
The control inputs sink higher currents (150 µA max) as a result
of the fast digital interfacing. Internal input protection of all
logic inputs is achieved by on-chip distributed diodes.
The AD7245A/AD7248A features a very low digital feedthrough
figure of 10 nV-s in a 5 V output range. This is due to the volt-
age mode configuration of the DAC. Most of the impulse is
actually as a result of feedthrough across the package.
INTERFACE LOGIC INFORMATION—AD7245ATable I shows the truth table for AD7245A operation. The part
contains two 12-bit latches, an input latch and a DAC latch. CS
and WR control the loading of the input latch while LDAC
controls the transfer of information from the input latch to the
DAC latch. All control signals are level triggered; and therefore,
