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AD7013ARS ,CMOS TIA IS-54 Baseband Receive PortSPECIFICATIONSV 1.23 Volts typREFReference Accuracy ±5 % maxReference Impedance 20 kΩ typLOGIC INPU ..
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ADC1175-50CIMT ,8-Bit, 50MSPS, 125mW A/D ConverterPin Descriptions and Equivalent Circuits (LLP pins in parentheses)PinSymbol Equivalent Circuit Desc ..
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AD7008AP20-AD7008JP50
CMOS DDS Modulator
REV.B
CMOS
DDS Modulator
FEATURES
Single +5 V Supply
32-Bit Phase Accumulator
On-Chip COSINE and SINE Look-Up Tables
On-Chip 10-Bit DAC
Frequency, Phase and Amplitude Modulation
Parallel and Serial Loading
Software and Hardware Power Down Options
20 MHz and 50 MHz Speed Grades
44-Pin PLCC
APPLICATIONS
Frequency Synthesizers
Frequency, Phase or Amplitude Modulators
DDS Tuning
Digital Modulationphase modulation, frequency modulation, and both in-phase and
quadrature amplitude modulation suitable for QAM and SSB
generation.
Clock rates up to 20 MHz and 50 MHz are supported. Fre-
quency accuracy can be controlled to one part in 4 billion.
Modulation may be effected by loading registers either through
the parallel microprocessor interface or the serial interface. A
frequency-select pin permits selection between two frequencies
on a per cycle basis.
The serial and parallel interfaces may be operated independently
and asynchronously from the DDS clock; the transfer control
signals are internally synchronized to prevent metastability prob-
lems. The synchronizer can be bypassed to reduce the transfer
latency in the event that the microprocessor clock is synchro-
nous with the DDS clock.
A power-down pin allows external control of a power-down
mode (also accessible through the microprocessor interface)
The AD7008 is available in 44-pin PLCC.
PRODUCT HIGHLIGHTLow PowerDSP/μP InterfaceCompletely Integrated
PRODUCT DESCRIPTIONThe AD7008 direct digital synthesis chip is a numerically con-
trolled oscillator employing a 32-bit phase accumulator, sine and
cosine look-up tables and a 10-bit D/A converter integrated on a
single CMOS chip. Modulation capabilities are provided for
AD7008–SPECIFICATIONS1NOTESOperating temperature ranges as follows: A Version: –40°C to +85°C; J Version: 0°C to +70°C.All dynamic specifications are measured using IOUT. 100% Production tested.fCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.VREF may be externally driven between 0 and VDD.Do not allow reference current to cause power dissipation beyond the limit of IAA + IDD shown above.
Specifications subject to change without notice.
(VAA = VDD = +5 V ± 5%; TA = TMIN to TMAX, RSET = 390 Ω, RLOAD = 1 Ω for
IOUT and IOUT, unless otherwise noted)
TIMING CHARACTERISTICS(VAA = VDD +5 V ± 5%; TA = TMIN to TMAX, unless otherwise noted)NOTEMay be reduced to 1t1 if LOAD is synchronized to CLOCK and Setup (t4) and Hold (t5) Times for LOAD to CLOCK are observed.
Figure 3.Parallel Port TimingFigure 2.Register Transfer Timing
Figure 1.Clock Synchronization Timing
AD7008
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VAA, VDD to GND
AGND to DGND
Digital I/O Voltage to DGND
Analog I/O Voltage to AGND
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 secs)
Junction Temperature
PLCC θJA Thermal Impedance
θJC Thermal Impedance
*Stresses above those listed under “Absolute Maximum Ratings” may cause
*AD7008/PCB DDS Evaluation Kit, assembled and tested. Kit includes an
PIN DESCRIPTION
MnemonicFunction
POWER SUPPLYVAAPositive power supply for the analog section. A 0.1 μF decoupling capacitor should be connected between VAA and
AGND. This is +5 V ± 5%.
AGNDAnalog Ground.
VDDPositive power supply for the digital section. A 0.1 μF decoupling capacitor should be connected between VDD
and DGND. This is +5 V ± 5%. Both VAA and VDD should be externally tied together.
DGNDDigital Ground; both AGND and DGND should be externally tied together.
ANALOG SIGNAL AND REFERENCEIOUT, IOUTCurrent Output. This is a high impedance current source. A load resistor should be connected between IOUT
and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND.
FS ADJUSTFull-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the mag-
nitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:
IOUTFULL-SCALE (mA) =
6233×VREFSETVREF = 1.27 V nominal RSET = 390 Ω typical
VREFVoltage Reference Input. A 0.1 μF decoupling ceramic capacitor should be connected between VREF and VAA.
There is an internal 1.27 volt reference which can be overdriven by an external reference if required. See
specifications for maximum range.
COMPCompensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF decoupling ceramic
capacitor should be connected between COMP and VAA.
DIGITAL INTERFACE AND CONTROLCLOCKDigital Clock Input for DAC and NCO. DDS output frequencies are expressed as a binary fraction of the fre-
quency of this clock. The output frequency accuracy and phase noise is determined by this clock.
FSELECTFrequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. Frequency selection can be done on a cycle-per-cycle basis. See Tables I, II and III.
LOADRegister load, active high digital Input. This pin, in conjunction with TC3–TC0, control loading of internal regis-
ters from either the parallel or serial assembly registers. The load pin must be high at least 1t1. See Table II.
TC3–TC0Transfer Control address bus, digital inputs. This address determines the source and destination registers that are
used during a transfer. The source register can either be the parallel assembly register or the serial assembly regis-
ter. The destination register can be any of the following: COMMAND REG, FREQ0 REG, FREQ1 REG,
PHASE REG or IQMOD REG. TC3–TC0 should be valid prior to LOAD rising and should not change until
LOAD falls. The Command Register can only be loaded from the parallel assembly register. See Table II.Chip Select, active low digital input. This input in conjunction with WR is used when writing to the parallel
assembly register.Write, active low digital input. This input in conjunction with CS is used when writing to the parallel assembly
register.
D7–D0Data Bus, digital inputs. These represent the low byte of the 16-bit data input port used to write to the 32-bit
parallel assembly register. The databus can configured for either a 8-bit or 16-bit MPU/DSP ports.
D15–D8Data Bus, digital inputs. These represent the high byte of the 16-bit data input port used to write to the 32-bit
parallel assembly register. The databus can be configured for either a 8-bit or 16-bit MPU/DSP ports. When the
databus is configured for 8-bit operation, D8–D15 should be tied to DGND.
SCLKSerial Clock, digital input. SCLK is used, in conjunction with SDATA, to clock data into the 32-bit serial assem-
bly register.
SDATASerial Data, digital input. Serial data is clocked on the rising edge of SCLK, Most Significant Bit (MSB) first.
SLEEPLow power sleep control, active high digital input. SLEEP puts the AD7008 into a low power sleep mode. Inter-
nal clocks are disabled, while also turning off the DAC current sources. A SLEEP bit is also provided in the
COMMAND REG to put the AD7008 into a low power sleep mode.
AD7008
PHASE
ACCUMULATOR
PHASE
SUMMATION
SIN/COS
SUMMATION
IOUT/IOUT
14 PIPELINE DELAYSFigure 7.AD7008 CMOS DDS Modulator (See Table I)
CS (27)
D0-D15
(19-26, 8-15)
RESET
LOAD (36)
(32-35)
WR (16)
SLEEP (37)
CLKFigure 8.AD7008 Register and Control Logic
Table II.Source and Destination Register*The Command Register can only be loaded from the parallel assembly registers.
Table III.AD7008 Control Registers*On power up, the Command Register should be configured by the user for the desired mode before operation.
Table IV.Command Register Bits*
Table I.Latency TableFSelect
NOTEAll latencies are reduced by 4t1 when CR3 = 1 (synchronizer disabled). 1t1 is
equal to one pipeline delay.
AD7008
CIRCUIT DESCRIPTIONThe AD7008 provides an exciting new level of integration for
the RF/Communications system designer. The AD7008 com-
bines the numerically controlled oscillator (NCO), SINE/CO-
SINE look-up tables, frequency, phase and IQ modulators, and
a digital-to-analog converter on a single integrated circuit.
The internal circuitry of the AD7008 consists of four main sec-
tions. These are:
Numerically Controlled Oscillator (NCO) + Phase Modulator
SINE and COSINE Look-Up Tables
In Phase and Quadrature Modulators
Digital-to-Analog Converter
The AD7008 is a fully integrated Direct Digital Synthesis
(DDS) chip. The chip requires one reference clock, two low-
precision resistors and six decoupling capacitors to provide
digitally created sine waves up to 25 MHz. In addition to the
generation of this RF signal, the chip is fully capable of a broad
range of simple and complex modulation schemes. These
modulation schemes are fully implemented in the digital domain
allowing accurate and simple realization of complex modulation
algorithms using DSP techniques.
THEORY OF OPERATIONSine waves are typically thought of in terms of their amplitude
form: a(t) = sin (ωt) or a(t) = cos (ωt). However, these are non-
linear and not easy to generate except through piece wise con-
struction. On the other hand, the angular information is linear
in nature. That is, the phase angle rotates though a fixed angle
for each unit of time. The angular rate depends on the fre-
quency of the signal by the traditional rate of: ω = 2 πf.
MAGNITUDE
PHASEFigure 9.
Knowing that the phase of a sine wave is linear and given a ref-
erence interval (clock period), the phase rotation for that period
can be determined.ΔPhase=ωdt
Solving for w:ΔPhase=2πf
Solving for f and substituting the reference clock frequency fordt
The AD7008 builds the output based on this simple equation.
A simple DDS chip will implement this equation with 3 major
subcircuits. The AD7008 has an extra section for I and Q
modulation.
Numerically Controlled Oscillator + Phase ModulatorThis consists of two frequency select registers, a phase accumu-
lator and a phase offset register. The main component of the
NCO is a 32-bit phase accumulator which assembles the phase
component of the output signal. Continuous time signals have a
phase range 0 to 2 π. Outside this range of numbers, the sinu-
soidal functions repeat themselves in a periodic manner. The
digital implementation is no different. The accumulator simply
scales the range of phase numbers into a multibit digital word.
The phase accumulator in the AD7008 is implemented with 32
bits. Therefore in the AD7008, 2 π = 232. Likewise, the ΔPhase
term is scaled into this range of numbers 0 ≤ ΔPhase ≤ 232 – 1.
Making these substitutions into the equation above: =ΔPhase×fCLOCK32where0≤ΔPhase<232
With a clock signal of 50 MHz and a phase word of 051EB852
hex: =51EB852×50MHz32=1.000000000931MHz
The input to the phase accumulator (i.e., the phase step) can be
selected either from the FREQ0 Register or FREQ1 Register,
and this is controlled by the FSELECT pin. The phase accu-
mulator in the AD7008 inherently generates a continuous 32-
bit phase signal, thus avoiding any output discontinuity when
switching between frequencies. This facilitates complex fre-
quency modulation schemes, such as GMSK.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit PHASE Register. The con-
tents of this register are added to the most significant bits of the
NCO.
Sine and Cosine Look-Up TablesTo make the output useful, the signal must be converted from
phase information into a sinusoidal value. Since phase informa-
tion maps directly into amplitude, a ROM look up table con-
verts the phase information into amplitude. To do this the
digital phase information is used to address a Sine/Cosine ROM
LUT. Only the most significant 12 bits are used for this pur-
pose. The remaining 20 bits provide frequency resolution and
minimize the effects of quantization of the phase to amplitude
conversion.
In Phase and Quadrature ModulatorsTwo 10-bit amplitude multipliers are provided allowing the easy
implementation of either Quadrature Amplitude Modulation
(QAM) or Amplitude Modulation (AM). The 20-bit IQMOD
Register is used to control the amplitude of the I (cos) and Q
(sin) signals. IQMOD [9:0] controls the I amplitude and
IQMOD [19:10] controls the Q amplitude.
The user should ensure that when summing the I and Q signals
the sum should not exceed the value that a 10-bit accumulator
