AD6645ASQ-105 Fast Delivery |IC PHOENIX CO.,LIMITED

AD6645ASQ-105 ,14-Bit, 80 /105 MSPS A/D ConverterAPPLICATIONS52-lead PowerQuad 4 (LQFP_PQ4) specified from –40°C toMultichannel, Multimode Receivers ..
AD6645ASQ-80 ,14-Bit, 80 MSPS A/D ConverterAPPLICATIONSlead PowerQuad 4 (LQFP_ED) specified from –40∞C to +85∞C.Multichannel, Multimode Receiv ..
AD6645ASQ-80 ,14-Bit, 80 MSPS A/D ConverterFEATURES generation in a wideband ADC family, preceded by the80 MSPS Guaranteed Sample Rate AD9042 ..
AD664AD-BIP ,Monolithic 12-Bit Quad DACspecifications.REV. CInformation furnished by Analog Devices is believed to be accurate andreliable ..
AD664BD-BIP ,Monolithic 12-Bit Quad DACFEATURESFour Complete Voltage Output DACs44-Pin PackageData Register Readback Feature“Reset to Zero ..
AD664BD-UNI ,Monolithic 12-Bit Quad DACSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
ADC0820BCN ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionELECTRICAL CHARACTERISTICS (VDD = +5V, VREF+ = +5V, VREF‘ = GND, RD-MODE, TA = TON to TMAX, unless ..
ADC0820BCV ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
ADC0820BCWM ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
ADC0820BCWMX ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
ADC0820CCD ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionELECTRICAL CHARACTERISTICS (VDD = +5V, VREF+ = +5V, VREF‘ = GND, RD-MODE, TA = TON to TMAX, unless ..
ADC0820CCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionBlock Diagram Ft BMW? HIT! HUT DIIVEIS PINS " WI? I4LSII ADCOB2O mama AID comm. ..

AD6645ASQ-105
14-Bit, 80 /105 MSPS A/D Converter
14-Bit, 80/105 MSPS
A/D Converter
REV.B
FEATURES
SNR = 75 dB, fIN 15 MHz up to 105 MSPS
SNR = 72 dB, fIN 200 MHz up to 105 MSPS
SFDR = 89 dBc, fIN 70 MHz up to 105 MSPS
100 dB Multitone SFDR
IF Sampling to 200 MHz
Sampling Jitter 0.1 ps
1.5 W Power Dissipation
Differential Analog Inputs
Pin Compatible to AD6644
Twos Complement Digital Output Format
3.3 V CMOS Compatible
DataReady for Output Latching
APPLICATIONS
Multichannel, Multimode Receivers
Base Station Infrastructure
AMPS, IS-136, CDMA, GSM, WCDMA
Single Channel Digital Receivers
Antenna Array Processing
Communications Instrumentation
Radar, Infrared Imaging
Instrumentation
PRODUCT DESCRIPTION
The AD6645 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter. All necessary functions, including
track-and-hold (T/H) and reference, are included on the chip to
provide a complete conversion solution. The AD6645 provides
CMOS compatible digital outputs. It is the fourth generation in a
wideband ADC family, preceded by the AD9042 (12-bit, 41MSPS),
the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644
(14-bit, 40 MSPS/65 MSPS).
Designed for multichannel, multimode receivers, the AD6645part of Analog Devices’ SoftCell® transceiver chipset. The
AD6645 maintains 100 dB multitone, spurious-free dynamic
range (SFDR) through the second Nyquist band. This break-
through performance eases the burden placed on multimode
digital receivers (software radios) that are typically limited by the
ADC. Noise performance is exceptional; typical signal-to-noise
ratio is 74.5 dB through the first Nyquist band.
The AD6645 is built on Analog Devices’ high speed complemen-
tary bipolar process (XFCB) and uses an innovative, multipass
circuit architecture. Units are available in a thermally enhanced
52-lead PowerQuad 4® (LQFP_PQ4) specified from –40°C to
+85°C at 80 MSPS and –10°C to +85°C at 105 MSPS.
PRODUCT HIGHLIGHTSIF Sampling
The AD6645 maintains outstanding ac performance up to
input frequencies of 200 MHz, suitable for multicarrier 3G
wideband cellular IF sampling receivers.
2. Pin Compatibility
The ADC has the same footprint and pin layout as the
AD6644, 14-Bit 40 MSPS/65 MSPS ADC.SFDR Performance and Oversampling
Multitone SFDR performance of –100 dBc can reduce the
requirements of high end RF components and allows the
use of receive signal processors such as the AD6620 or
AD6624/AD6624A.
FUNCTIONAL BLOCK DIAGRAM
AD6645–SPECIFICATIONS
DC SPECIFICATIONS
NOTESVREF is provided for setting the common-mode offset of a differential amplifier such as the AD8138 when a dc-coupled analog input is required. VREF should be
buffered if used to drive additional circuit functions.Specified for dc supplies with linear rise time characteristics.
Specifications subject to change without notice
DIGITAL SPECIFICATIONS
NOTES
1All ac specifications tested by driving ENCODE and ENCODE differentially.
2The functionality of the Overrange bit is specified for a temperature range of 25°C to 85°C only.
(AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.)
(AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.)
AD6645
AC SPECIFICATIONS1
SINAD
WORST HARMONIC (Second or Third)
WORST HARMONIC (Fourth or Higher)
TWO TONE SFDR @30.5 MHz
TWO TONE IMD REJECTION
NOTESAll ac specifications tested by driving ENCODE and ENCODE differentially.Analog input signal power swept from –10 dBFS to –100 dBFS.F1 = 30.5 MHz, F2 = 31.5 MHz.F1 = 55.25 MHz, F2 = 56.25 MHz.F1 = 69.1 MHz, F2 = 71.1 MHz.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
(AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless
otherwise noted.)
(AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted.)
AD6645
(AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade,
CLOAD = 10 pF, unless otherwise noted.)SWITCHING SPECIFICATIONS (continued)
NOTESSeveral timing parameters are a function of tENC and tENCH.ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter, tE_RL = tH_E.DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.DataReady to DATA Delay (tH_DR and tS_DR) is calculated relative to rated speed grade and is dependent on tENC and duty cycle.
Specifications subject to change without notice.
Figure 1.Timing Diagram
THERMAL CHARACTERISTICS
52-Lead Power Quad 4 LQFP_PQ4
�JA = 23°C/W Soldered Slug, No Airflow
�JA = 17°C/W Soldered Slug, 200 LFPM Airflow
�JA = 30°C/W Unsoldered Slug, No Airflow
�JA = 24°C/W Unsoldered Slug, 200 LFPM Airflow
�JC = 2°C/W Bottom of Package (Heatslug)
Typical 4-Layer JEDEC Board Horizontal Orientation
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD6645
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
* Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability
of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute
maximum rating conditions for an extended period of time may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.
II.100% production tested at 25°C and guaranteed by design
and characterization at temperature extremes.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
AD6645
PIN CONFIGURATION
GND
GND
GNDGND
GND
GND
DRYD13 (MSB)D12D11D10
GNDD5D4
DVCC
GND
VREF
GND
ENC
ENC
GND
AVCC
AVCC
GND
AIN
AIN
GND
D0 (LSB)
DMID
GND
DVCC
OVR
DNC
AVCC
GND
AVCC
GND
DNC = DO NOT CONNECT
PIN FUNCTION DESCRIPTIONS
37–41, 44–50
*The functionality of the overrange bit is specified for a temperature range of 25°C to 85°C only.
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees
out of phase. Peak-to-peak differential is computed by rotating
the inputs’ phase 180 degrees and taking the peak measurement
again. Then the difference is computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing implica-
tions of changing tENCH in text. At a given clock rate, these
specs define an acceptable ENCODE duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Noise (For Any Range Within the ADC)
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question; SNR is the value for the particular
input level; and Signal is the signal level within the ADC reported
in dB below full scale. This value includes both thermal and
quantization noise.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power
supply voltage.
Power Supply Rise Time
The time from when the dc supply is initiated until the supply
output reaches the minimum specified operating voltage for the
ADC. The dc level is measured at the supply pin(s) of the ADC.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component
may or may not be a harmonic. May be reported in dBc (i.e.,
degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Two Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Two Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product, may be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.
AD6645
EQUIVALENT CIRCUITS
Figure 2.Analog Input Stage
Figure 3.Encode Inputs
Figure 4.Compensation Pin, C1 or C2
Figure 5.Digital Output Stage
Figure 6.2.4 V Reference
Figure 7.DMID Reference
TPC 1.Single Tone @ 2.2 MHz
TPC 2.Single Tone @ 15.5 MHz
TPC 3.Single Tone @ 29.5 MHz
TPC 4.Single Tone @ 69.1 MHz
TPC 5.Single Tone @ 150 MHz
TPC 6.Single Tone @ 200 MHz
AD6645
TPC 7.Noise vs. Analog Frequency
TPC 8.Harmonics vs. Analog Frequency
TPC 9.Noise vs. Analog Frequency (IF)
TPC 10.Harmonics vs. Analog Frequency (IF)
TPC 11.Single Tone SFDR @ 30.5 MHz
TPC 12.Single Tone SFDR @ 69.1 MHz

Partno	Mfg	Dc	Qty	Available	Descript
AD6645ASQ-105 \|AD6645ASQ105	ADI	N/a	17	avai	14-Bit, 80 /105 MSPS A/D Converter